Patents by Inventor Eon Soo JANG
Eon Soo JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088118Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Manho LEE, Eunseok SONG, Keung Beum KIM, Kyung Suk OH, Eon Soo JANG
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Patent number: 11862618Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: GrantFiled: July 7, 2021Date of Patent: January 2, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Manho Lee, Eunseok Song, Keung Beum Kim, Kyung Suk Oh, Eon Soo Jang
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Publication number: 20220165721Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.Type: ApplicationFiled: July 7, 2021Publication date: May 26, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Manho LEE, Eunseok SONG, Keung Beum KIM, Kyung Suk OH, Eon Soo JANG
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Patent number: 11205604Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.Type: GrantFiled: October 1, 2018Date of Patent: December 21, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Choon Kim, Woo Hyun Park, Eon Soo Jang, Young Sang Cho
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Patent number: 10546844Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.Type: GrantFiled: November 3, 2016Date of Patent: January 28, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Choon Kim, Eon-Soo Jang, Eun-Hee Jung, Hyon-Chol Kim, Byeong-Yeon Cho
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Publication number: 20190237382Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.Type: ApplicationFiled: October 1, 2018Publication date: August 1, 2019Inventors: Jae Choon KIM, Woo Hyun PARK, Eon Soo JANG, Young Sang CHO
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Patent number: 9842799Abstract: A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side of the lower package and covers a portion of the lower semiconductor chip, and an upper package is on the lower package and is laterally spaced apart from the heat dissipation part.Type: GrantFiled: October 16, 2015Date of Patent: December 12, 2017Assignee: Samsung Electronics Co., Ltd.Inventor: Eon Soo Jang
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Patent number: 9704815Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.Type: GrantFiled: May 16, 2016Date of Patent: July 11, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi-Na Choi, Young-Deuk Kim, Jae-Choon Kim, Eon-Soo Jang, Hee-Jung Hwang
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Publication number: 20170154878Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.Type: ApplicationFiled: November 3, 2016Publication date: June 1, 2017Inventors: Jae-Choon Kim, Eon-Soo Jang, Eun-Hee Jung, Hyon-Chol Kim, Byeong-Yeon Cho
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Patent number: 9653373Abstract: A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film between the semiconductor chip and the heat spreader, and a through-hole passing through the heat spreader. The heat spreader includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader.Type: GrantFiled: December 21, 2015Date of Patent: May 16, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Choon Kim, Heejung Hwang, Eon Soo Jang
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Patent number: 9583430Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.Type: GrantFiled: August 11, 2014Date of Patent: February 28, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyol Park, Jichul Kim, Yunhyeok Im, Eon Soo Jang
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Publication number: 20160372423Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.Type: ApplicationFiled: May 16, 2016Publication date: December 22, 2016Inventors: Mi-Na CHOI, Young-Deuk KIM, Jae-Choon KIM, Eon-Soo JANG, Hee-Jung HWANG
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Publication number: 20160300774Abstract: A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film between the semiconductor chip and the heat spreader, and a through-hole passing through the heat spreader. The heat spreader includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader.Type: ApplicationFiled: December 21, 2015Publication date: October 13, 2016Inventors: Jae Choon Kim, Heejung Hwang, Eon Soo Jang
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Patent number: 9391009Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.Type: GrantFiled: May 29, 2014Date of Patent: July 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Eon Soo Jang, Kyol Park, Jongwoo Park, Jin-Kwon Bae, Yunhyeok Im, Jichul Kim, Soojae Park
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Publication number: 20160118366Abstract: A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side of the lower package and covers a portion of the lower semiconductor chip, and an upper package is on the lower package and is laterally spaced apart from the heat dissipation part.Type: ApplicationFiled: October 16, 2015Publication date: April 28, 2016Inventor: Eon Soo Jang
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Patent number: 9190338Abstract: A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.Type: GrantFiled: February 25, 2014Date of Patent: November 17, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyol Park, Yunhyeok Im, Eon Soo Jang
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Patent number: 9029998Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.Type: GrantFiled: April 2, 2014Date of Patent: May 12, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Eon Soo Jang, Kyol Park, Yunhyeok Im
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Publication number: 20150115467Abstract: The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.Type: ApplicationFiled: August 11, 2014Publication date: April 30, 2015Inventors: Kyol PARK, JICHUL KIM, YUNHYEOK IM, Eon Soo JANG
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Publication number: 20150054148Abstract: According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.Type: ApplicationFiled: May 29, 2014Publication date: February 26, 2015Inventors: Eon-Soo JANG, Kyol PARK, Jongwoo PARK, Jin-Kwon BAE, Yun-Hyeok IM, Ji-Chul KIM, Soojae PARK
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Publication number: 20140353813Abstract: A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.Type: ApplicationFiled: February 25, 2014Publication date: December 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyol Park, Yunhyeok Im, Eon Soo Jang