Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

Abstract: A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.

Abstract: A handheld laser-based vehicle speed measurement device incorporating on-board data storage with GPS, compass, excess panning detection, and voice recognition technology, as well as, recording minimum and maximum speeds of a plurality of vehicles along a roadway and calculating the 85th percentile speed.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

Abstract: The disclosure relates to chemokine CXCR4 receptor modulators and uses related thereto. The receptor modulators can be formulated to form pharmaceutical compositions comprising the disclosed compounds or pharmaceutically acceptable salts or prodrugs thereof. The compositions may be used for managing CXCR4 related conditions, typically prevention or treatment of viral infections abnormal cellular proliferation, retinal degeneration, inflammatory diseases, or as an immunostimulant or immunosuppressant or for managing cancer and may be administered with another active ingredient such as an antiviral agent or chemotherapeutic agent.

Abstract: Embodiments disclosed herein include a semiconductor structure for reducing contact to contact shorting. The semiconductor structure may include a gate cut region with a liner and a dielectric core confined within a first lateral side of the liner and a second lateral side of the liner. The semiconductor structure may also include a first source/drain (S/D) contact overlapping the first lateral side and the dielectric core. The first S/D may include a line-end that contacts the second lateral side of the liner.

Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.

Abstract: A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.

Abstract: Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.

Abstract: A staple gun and a method of using the same. A stapling mechanism in the housing is activated to deliver a staple through an aperture in a housing wall and drive the staple into a surface around a stack of one or more electric cables. The gun includes a reciprocating cable guide for centering the gun on the stack of cables and closing a safety switch to permit the gun's trigger to be activated. A spacer extending outwardly from the housing wall rests on the upper surface of the cable stack. The spacer and a bumper that engages a hammer of the stapling mechanism provide for automatic depth adjustment when driving the staple into the surface. A reciprocating cable guard extending outwardly from the housing wall is positioned between the stack of cables and the staple to aid in preventing the staple from piercing the cable.

Abstract: X-ray transparent insulation can be sandwiched between an x-ray window and a ground plate. The x-ray transparent insulation can include aluminum nitride, boron nitride, or polyetherimide. The x-ray transparent insulation can include a curved side. The x-ray transparent insulation can be transparent to x-rays and resistant to x-ray damage, and can have high thermal conductivity. An x-ray window can have high thermal conductivity, high electrical conductivity, high melting point, low cost, and matched coefficient of thermal conductivity with the anode. The x-ray window can be made of tungsten. For consistent x-ray spot size and location, a focusing plate and a filament can be attached to a cathode with an open channel of the focusing plate aligned with a longitudinal dimension of the filament. Tabs of the focusing plate bordering the open channel can be bent to align with a location of the filament.

Abstract: A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.

Abstract: Systems and methods for reducing the amount of messages transmitted in large-scale distributed mesh networks are disclosed. Network components include transceivers and memory storing instructions which, when executed by a processing unit, reduce transmissions made by the transceiver within the network. The instructions executed by processing unit could (1) create an expiration parameter to limit the number of times a signal is retransmitted, (2) form groups of network components from which one or a few of the group network components are designated to respond on behalf of the group, (3) keep advertising transmissions dormant by default until called upon, (4) employ a time delay parameter for a time interval in which no transmission may be made, and (5) include message IDs in control signals that are transmitted.

Abstract: A blender system that includes a base that is select ively and operatively engaged with a container is shown and described herein. The base may include a near field communications chip that may communicate with a near field communications chip of a container. The base also includes a motor that is selectively and operatively engaged with a blade disposed within the container.

Abstract: A system including a valve. The valve includes a valve body having an interior volume and a bore along a first axis. A stem extends along a second axis and a flow control element couples to the stem. The stem selectively moves the flow control element through the interior volume between a closed position and an open position relative to the bore. A valve insert system retains a pressurized lubricant in the interior volume.

Abstract: A shield around an x-ray tube, a voltage multiplier, or both can improve the manufacturing process by allowing testing earlier in the process and by providing a holder for liquid potting material. The shield can also improve voltage standoff. A shielded x-ray tube can be electrically coupled to a shielded power supply.

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Abstract: A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.