Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.

Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.

Abstract: The invention concerns the field of cell culture technology. The invention describes production host cell lines comprising vector constructs comprising a DHFR expression cassette. Those cell lines have improved growth characteristics in comparison to DHFR-deficient or DHFR-reduced cell lines such as CHO DG44 and CHO DUKX-B11. The invention especially concerns two cell lines, a representative of each cell line is deposited with the DSMZ under the number DSM ACC2909 (CHOpper® Discovery) and DSM ACC2910 (CHOpper® Standard). The invention further concerns a method of producing proteins using the cells generated by the described method.

Abstract: This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection circuit, a delay comparison circuit, and a control circuit. The plurality of delay lines can generate a plurality of delayed clock signals, and the selection circuit can include a plurality of inputs configured to receive at least the plurality of delayed clock signals. The selection circuit can generate a first output clock signal and a second output clock signal by selecting amongst signals received at the plurality of inputs based on a state of a selection control signal. The delay comparison circuit can compare a delay of the first output clock signal to a delay of the second output clock signal and can generate a delay comparison such as a pass/fail flag based on the result. The control circuit can generate the selection control signal.

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract: Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.

Abstract: Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then initiate a quiescent mode of operation. Quiescent operation may be achieved by breaking a feedback loop associated with the DLL or PLL to prevent updates to a variable delay line associated with the DLL and/or to a variable frequency oscillator associated with the PLL. An output clock phase associated with the DLL or PLL may thus be held substantially constant following a DLL initialization period. Additional embodiments are disclosed and claimed.

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract: The invention concerns the field of cell culture technology. It concerns a method of improving cell growth, especially the growth of biopharmaceutical producer host cells. The invention further concerns a method of producing proteins using the cells generated by the described method.

Abstract: The invention concerns the field of protein production and cell culture technology. CERT is identified as a novel in vivo PKD substrate. Phosphorylation on serine 132 by PKD decreases the affinity of CERT towards its lipid target phosphatidylinositol 4-phosphate at Golgi membranes and reduces ceramide transfer activity, identifying PKD as a regulator of lipid homeostasis. The present invention shows that CERT in turn is critical for PKD activation and PKD dependent protein cargo transport to the plasma membrane. The interdependence of PKD and CERT is thus a key to the maintenance of Golgi membrane integrity and secretory transport.

Abstract: The invention concerns the field of protein production and cell culture technology. CERT is identified as a novel in vivo PKD substrate. Phosphorylation on serine 132 by PKD decreases the affinity of CERT towards its lipid target phosphatidylinositol 4-phosphate at Golgi membranes and reduces ceramide transfer activity, identifying PKD as a regulator of lipid homeostasis. The present invention shows that CERT in turn is critical for PKD activation and PKD dependent protein cargo transport to the plasma membrane. The interdependence of PKD and CERT is thus a key to the maintenance of Golgi membrane integrity and secretory transport.

Abstract: The invention concerns the field of protein production and cell culture technology. CERT is identified as a novel in vivo PKD substrate. Phosphorylation on serine 132 by PKD decreases the affinity of CERT towards its lipid target phosphatidylinositol 4-phosphate at Golgi membranes and reduces ceramide transfer activity, identifying PKD as a regulator of lipid homeostasis. The present invention shows that CERT in turn is critical for PKD activation and PKD dependent protein cargo transport to the plasma membrane. The interdependence of PKD and CERT is thus a key to the maintenance of Golgi membrane integrity and secretory transport.

Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.

Abstract: The invention concerns the field of protein production and cell culture technology. CERT is identified as a novel in vivo PKD substrate. Phosphorylation on serine 132 by PKD decreases the affinity of CERT towards its lipid target phosphatidylinositol 4-phosphate at Golgi membranes and reduces ceramide transfer activity, identifying PKD as a regulator of lipid homeostasis. The present invention shows that CERT in turn is critical for PKD activation and PKD dependent protein cargo transport to the plasma membrane. The interdependence of PKD and CERT is thus a key to the maintenance of Golgi membrane integrity and secretory transport.

Abstract: The invention concerns the field of cell culture technology. The invention describes production host cell lines comprising vector constructs comprising a CERT S132 A expression cassette. Those cell lines have improved growth characteristics and high CERT S132A expression levels. The invention especially concerns two cell lines deposited with the DSMZ under the number DSM ACC2989 (CHO/CERT 2.20) and DSM AC-C2990 (CHO/CERT 2.41). The invention further concerns a method of generating such preferred production host cells and a method of producing proteins using the two cell lines deposited with the DSMZ under the number DSM ACC2989 (CHO/CERT 2.20) and DSM ACC2990 (CHO/CERT 2.41).

Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.

Abstract: The invention concerns the field of protein production and cell culture technology. It describes a method of producing a heterologous protein of interest in a cell comprising a. Increasing the expression or activity of a secretion enhancing gene, and b. Increasing the expression or activity of an anti-apoptotic gene, and c. Effecting the expression of said protein of interest, whereby the secretion enhancing gene is a gene encoding a protein whose expression or activity is induced during one of the following cellular processes: plasma-cell differentiation, unfolded protein response (UPR), endoplasmic reticulum overload response (EOR).

Abstract: Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal.

Abstract: A method and apparatus for cleaning printed circuit boards are provided. The method includes providing a cleaning apparatus with a housing having a conveyance mechanism for carrying printed circuit boards through the housing. The cleaning apparatus has at least a prewash station, a wash station and a final rinse station therein. The printed circuit boards are carried on the conveyance mechanism to the prewash station. A plurality of fluidic oscillator nozzles of the prewash station are utilized to direct liquid onto the printed circuit boards. Each fluidic oscillator nozzle outputs a stream of liquid with an instantaneous direction that oscillates back and forth relative to a nozzle axis over time.

Abstract: Memory systems and devices are provided. One memory system includes a controller configured to be coupled to a plurality of computing devices, a plurality of Multi-Level Cell (MLC) devices coupled to the controller, and a Single-Level Cell (SLC) device coupled to the controller and the plurality of MLC devices. The MLC devices are configured to split the storage of data across the plurality of MLC devices and the SLC device is configured to function as a parity device for the data. A memory device includes a controller, a plurality of MLC FLASH devices, and a SLC FLASH device. The MLC FLASH devices are configured to split the storage of data across the plurality of MLC FLASH devices and the SLC FLASH device is configured to function as a parity device for the data. Also provided are computing devices including the above memory device.