Patents by Inventor Eric Dahlen
Eric Dahlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7723816Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.Type: GrantFiled: August 6, 2008Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7675164Abstract: A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the complementary fold having a counterclockwise fold and a clockwise fold as seen from the side. A first chip back surface of a first chip and a second chip back surface of a second chip are in thermal contact with a particular heat sink fin, that is, sharing the same heat sink fin. Thermal contact between the chips and heat sink fins is effected by force, by thermally conducting adhesive, by thermal grease, or by a combination of force and/or thermally conducting adhesive and/or thermal grease.Type: GrantFiled: March 6, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7673093Abstract: A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. A daisy chain of memory chips can include memory chips on multiple carriers, or the daisy chain of memory chips can all be attached to a single carrier.Type: GrantFiled: July 26, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20100032799Abstract: A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.Type: ApplicationFiled: August 6, 2008Publication date: February 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7660942Abstract: A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.Type: GrantFiled: July 26, 2006Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7660940Abstract: A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.Type: GrantFiled: July 26, 2006Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20100024202Abstract: This invention utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.Type: ApplicationFiled: August 1, 2008Publication date: February 4, 2010Inventors: Andrew Benson Maki, Gerald Keith Bartley, Philip Raymond Germann, Mark Owen Maxson, Darryl John Becker, Paul Eric Dahlen, John Edward Sheets, II
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Publication number: 20100019385Abstract: Methods and structures are provided for implementing reduced hot spot thermal effects for silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. A thermal conductive path is built to reduce thermal effects of a hotspot area in the active layer and extends from the active layer to the backside of the SOI structure. A trench etched from the topside to the active layer, and is filled with a thermal connection material. A thermal connection from a backside of the SOI structure includes an opening etched into the silicon substrate layer from the backside and filled with a thermal connection material.Type: ApplicationFiled: July 23, 2008Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Publication number: 20090300411Abstract: A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson
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Publication number: 20090300291Abstract: A method and apparatus implement cache coherency and reduced latency using multiple controllers for a memory system, and a design structure is provided on which the subject circuit resides. A first memory controller uses a first memory as its primary address space, for storage and fetches. A second memory controller is also connected to the first memory. A second memory controller uses a second memory as its primary address space, for storage and fetches. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. A request and send sequence of the invention sends data directly to a requesting memory controller eliminating the need to re-route data back through a responding controller, and improving the latency of the data transfer.Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson
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Patent number: 7627711Abstract: A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the request is directed to, and transmits an address/command word recognizable by the correct memory chip. The memory controller sends write data words to the daisy chain of memory chips that can be associated by the correct memory chip for writing into the correct memory chip. The memory controller receives read data words from the daisy chain of memory chips and returns the read data to the processor. The memory controller transmits a bus clock to the daisy chain of memory chips for controlling transmission of address/command words and data words.Type: GrantFiled: July 26, 2006Date of Patent: December 1, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7620763Abstract: A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.Type: GrantFiled: July 26, 2006Date of Patent: November 17, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7617350Abstract: A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to a memory chip on a second carrier.Type: GrantFiled: July 26, 2006Date of Patent: November 10, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20090273098Abstract: A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the first variant of the chip. The first and second variants of the chip are attached to the carrier such that a vertical surface (side) of the first variant of the chip faces a corresponding vertical surface of the second variant of the chip. A circuit on the first variant of the chip is electrically connected to a corresponding circuit on the second variant of the chip.Type: ApplicationFiled: May 1, 2008Publication date: November 5, 2009Inventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7577811Abstract: A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The memory controller determines current access time information on a memory chip by sending a command to the memory chip. The memory chip returns a data word containing the current access time information. Alternatively, the memory controller transmits an address/command word to the memory chip and, after completing an access, transmits a responsive data word to the memory controller. The memory controller determines the access time information using the interval from transmission of the address/command word to reception of the responsive data word.Type: GrantFiled: July 26, 2006Date of Patent: August 18, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7553696Abstract: A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected between a predefined pair of adjacent columns in the solder column grid array suspended between the printed circuit board and the first level package.Type: GrantFiled: August 29, 2006Date of Patent: June 30, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7545664Abstract: A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Data to be written to a memory chip is sent as part of the address/command word, or is transferred on an outgoing data bus chain. Data read from a memory chip is transferred on an incoming data bus chain. Access timing on a memory chip is determined by a self time block on the memory chip.Type: GrantFiled: July 26, 2006Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Patent number: 7546410Abstract: A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be accessed. The ring oscillator includes a bit line that is periodically charged and a memory element that subsequently discharges the bit line. The memory chip has a data bus interface having a number of bits. The data bus interface has a first number of bits apportioned to write data and a second number of bits apportioned to read data. The first number of bits and the second number of bits is programmable.Type: GrantFiled: July 26, 2006Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson
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Publication number: 20090138832Abstract: Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.Type: ApplicationFiled: November 21, 2008Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald Keith Bartley, Darryl John Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson, Trevor Joseph Timpane
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Patent number: 7490186Abstract: A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a data bus chain having a number of data bus bits. The data bus chain has a first portion of data bus bits dedicated to transmitting write data from the memory controller to a memory chip. The data bus chain has a second portion of data bus bits dedicated to transmitting read data from a memory chip to the memory controller. Apportionment of data bus bits between the first portion and the second portion is programmable. Programming is done by pin connection, scanning of a value, or by request from a processor coupled to the memory controller.Type: GrantFiled: July 26, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki, Mark Owen Maxson