Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.

Abstract: A method and apparatus are provided for implementing direct attenuation loss measurement in an electronic package. A sinusoidal voltage source signal of a selected frequency is coupled to an embedded transmission line test structure in the electronic package. Receive circuitry is coupled to the transmission line test structure for detecting amplitude of a received sinusoidal voltage source signal to identify attenuation loss through the transmission line test structure. An identified attenuation loss of the transmission line test structure is compared with a threshold value for verifying acceptable attenuation of the electronic package transmission line test structure.

Abstract: A method and a probe structure are provided for implementing multiple signals probing of a printed circuit board. A probe structure is formed on an outside surface of the printed circuit board. A resistor is electrically connected with an associated via with a signal to be monitored. A path to a predefined probe location for monitoring the signal is defined from the resistor using the probe structure.

Abstract: Some embodiments of the invention accurately account for power dissipation in memory systems that include individual memory modules by keeping track of the number of read requests, the number of write requests, and the number of activate requests that are applied to the individual memory modules during selected time periods. If the sum of these totals exceeds a threshold level, the embodiments throttle the memory system, either by throttling the entire memory system based in response to the most active memory module, or by throttling individual memory modules as needed. Other embodiments of the invention may assign the same or different weights to activate requests, read requests, and write requests. Other embodiments are described and claimed.

Abstract: In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

Abstract: A method and apparatus are provided for implementing automated electronic package transmission line characteristic impedance verification. A sinusoidal voltage source is coupled to a transmission line test structure for generating a selected frequency. Impedance measuring circuitry is coupled to the transmission line test structure for measuring an input impedance with an open-circuit termination and a short-circuit termination. Characteristic impedance calculation circuitry is coupled to the impedance measuring circuitry receiving the input impedance measured values for the open-circuit termination and the short-circuit termination for calculating characteristic impedance. Logic circuitry is coupled to the characteristic impedance calculation circuitry for comparing the calculated characteristic impedance with threshold values for verifying acceptable electronic package transmission line characteristic impedance.

Abstract: Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective physical design is generated for customized passive devices, a logic chip, and a chip carrier. Silicon devices are fabricated utilizing the generated respective physical design for customized passive devices and the logic chip and a carrier package is fabricated. The fabricated silicon devices are assembled on the carrier package.

Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also include nominal values. Models that meet the bounding electrical criteria may be used in modeling the transmission line while models that do not meet the bounding electrical criteria are not used.

Abstract: Methods and apparatus are disclosed for improved via utilization on printed wiring boards (PWB). A via in a PWB typically transfers a single electrical signal from one signal plane to another wiring plane on the PWB. The present invention provides for more than a single signal to be transferred through a single via having a conducting wall. The conducting wall of the via is divided into more than one conducting portion, each portion capable of conducting a signal from one signal plane to another signal plane.

Abstract: A method and structure are provided for implementing enhanced differential signal trace routing in a printed circuit board. The structure includes a differential signal trace pair and a differential pair via arrangement including a pair of vias. The pair of vias is coupled to the differential signal trace pair for routing the differential signal trace pair between first and second layers of the PCB. The vias are laterally offset by a predefined spacing sharing overlapping clearance holes and are diagonally oriented to allow minimal separation of the differential signal trace pair and matched signal trace lengths of the differential signal trace pair.

Abstract: A method and embedded bus bar structure are provided for implementing power distribution in an electronic system. A stiffener includes an embedded power bus bar structure for distributing power. The embedded power bus bar structure has a predefined pattern within a selected area of the stiffener. The selected area is separated from at least one predefined area. A printed circuit board is mounted to the stiffener and electrically connected to the embedded power bus bar structure. The embedded power bus bar structure can include multiple spaced apart power bus bars, enabling the power distribution of multiple voltage levels. The predefined pattern of the embedded power bus bar structure within the selected area of the stiffener is separated from each predefined site for a Land Grid Array (LGA).

Abstract: A data transfer method and apparatus are provided for transferring data in a computer system on a high-speed synchronous multi-drop bus. Multiple devices including at least a first group of a plurality of devices and a second group of at least one device are connected to the high-speed synchronous multi-drop bus. To transfer data between devices in the first group, a first unidirectional data valid signal is applied to each device in the second group. The data from a sending device in the first group is transferred to a designated device in the second group. A second unidirectional data valid signal is applied to each device in the first group. The data is transferred from the designated device in the second group to a selected device in the first group.