Abstract: A method and a system are provided for maintaining a virtual-wait queue that controls access by customers to a physical resource such as a restaurant table. The method and system are especially adapted for use by customers operating Internet-enabled wireless devices. The system operates by maintaining a virtual-wait queue data structure capable of storing a plurality of entries. Each entry is representative of a customer. The system accepts an instruction from a premises I/O device indicating to either add or delete an entry to the data structure. The system also accepts an instruction from a network connection to either add or delete the remote customer into or from the virtual wait queue. The virtual wait queue system indicates to the remote customer the estimated time left in the queue, freeing the customer from the need to wait in line.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: The present invention provides a processing apparatus and methods for the extraction of user information streams from a composite CDMA waveform. The apparatus and methods increase CDMA system capacity by orthogonalizing an individual user's signal from thermal noise components, multi-access interference, and spatially diverse but non-orthogonal coded components. The present invention exploits both the temporal diversity and the spatial diversity present in the received composite CDMA waveform to increase performance. The smart antenna multiuser detector makes use of blind-block-adaptive nonlinear optimization strategies, which are used to separate user signal components from a composite CDMA waveform by jointly processing in both a chip (code) and spatial domain.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and multiply pipelined machines, branches can potentially cause the pipeline to stall because the branch alters the instruction flow, leaving the prefetch buffer and first pipeline stages with discarded instructions. This has the effect of reducing system performance by making the branch instruction appear to require multiple cycles to execute. The improved branch cache differs from conventional branch caches. In particular, the improved cache is not used for branch prediction, but rather, the improved branch cache avoids stalls by providing data that will be inserted into the pipeline stages that would otherwise have stalled when a branch is taken.

Abstract: Methods and apparatus for allowing a packet data connection to be established by sending an indication of a network address through a telephony path. In a first embodiment, a protocol stack initiates the establisment of an Internet connection by sending a data segment through a public switched telephone network (PSTN) telephony path and then operates and maintains the Internet connection on separate packet connection. Dialing digits are used to indicate the address of a remote computer or wireless device via the telephony path. This invention also enables mixed PSTN/internet multimedia telephone calls. In an exemplary embodiment, when a point-to-point telephone PSTN connection is established, a screen of information automatically appears at one or both ends of the connection via the Internet.

Abstract: An apparatus and method for spread spectrum multiuser communication receivers is disclosed that includes, an adaptive filter adapted to minimize a block error function, wherein the filter tap weights are updated according to a non-linear optimization algorithm adapted for block processing of time-varying data.

Abstract: The present invention is an optical signal processing apparatus which centers around an active optical filter. The active optical lattice filter permits ultra-high bandwidth signal processing of optical signals. The filter utilizes a lattice arrangement of optical amplifiers and interfaces which feed and reinforce each other. The lattice sections are constructed of a semiconductive material so that the device may be used as an optoelectronic component of an optical communications system. A control voltage is applied to each optical amplifier thereby enabling a user to electronically control and tune the optical transfer function of the device. The lattice parameters may be adjusted to produce an tunable oscillation to produce a precision optical line frequency. Precision optical line frequencies are useful in dense wavelength division multiplexers. Also, the lattice parameters may be adjusted to produce very high-Q optical filters are needed to construct dense wavelength division demultiplexers.

Abstract: A pipelined processor includes a branch acceleration technique which is based on an improved branch cache architecture. In one exemplary embodiment, the present invention has an instruction pipeline comprising a plurality of stages, each stage initially containing first data. A branch cache module stores at least a portion of the first data from one or more of the pipeline stages, and a branch cache control unit causes the branch cache module to store at least portion of the first data from one or more of the pipeline stages in response to execution of a cacheable branch instruction which triggers a cache miss, and causes the branch cache module to restore second data to one or more of the pipeline stages in response to a cache hit. The present invention also discloses methods for controlling the branch cache and for reducing pipeline stalls caused by branching.

Abstract: A reduced complexity precoder provides an efficient method and structure to precode a vector-signal-point sequence for transmission through a band-limited channel. The precoder enables a block-oriented receiver to recover an underlying data stream in the presence of inter-symbol interference and noise. The precoder structure is applicable to multicarrier systems such as DMT (discrete multitone) or related transform domain and vector communication systems. The inventive precoder reduces the cost of preceding by an order of magnitude and eliminates the need for a cyclic prefix in DMT and related communication systems. Related multicarrier transmitter and receiver structures and methods which reduce computation, increase transmission bandwidth and reduce transmission power are also developed.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory.

Abstract: An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory.

Abstract: A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream.