Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the registers and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.

Abstract: A very long instruction word (VLIW) processor exploits program level parallelism as well as instruction level parallelism. Unlike prior VLIW machines which obtain speed advantages using instruction level parallelism, the present processor exploits the parallelism inherent in a VLIW processor by providing new instruction level mechanisms to separate processor execution into parallel threads. This separation allows greater hardware use because more than one program can exploit instruction level parallelism on the system at the same time. A first program and a second program execute concurrently such that the second program executes using resources and cycles that would have been wasted by the first program. This construct is especially useful where the second program is an interrupt service routine because the interrupt service routine can be threaded through the machine with high or low priority while the functional units still process the first program stream.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and multiply pipelined machines, branches can potentially cause the pipeline to stall because the branch alters the instruction flow, leaving the prefetch buffer and first pipeline stages with discarded instructions. This has the effect of reducing system performance by making the branch instruction appear to require multiple cycles to execute. The improved branch cache differs from conventional branch caches. In particular, the improved cache is not used for branch prediction, but rather, the improved branch cache avoids stalls by providing data that will be inserted into the pipeline stages that would otherwise have stalled when a branch is taken.

Abstract: A direct memory access and direct register access (DMA/DRA) controller and method are used on microprocessors, microcontrollers and digital signal processors which incorporate shadow register sets or register windows or both. The DMA/DRA controller is coupled to the processor's data paths so as to transfer data between the register and memory in burst and in cycle-steal modes. The DMA/DRA controller enables the processor to perform single-cycle register set save and restore operations by extending the effective depth of the shadow register set by creating virtual register sets in memory. The DMA/DRA subsystem interacts with the caches and other memory traffic controllers to perform the register set transfers before they are needed making use of otherwise unused external memory cycles. Using this invention, delays associated with register saving and restoring can be largely eliminated without the need for unduly large and costly internal sets of register files.

Abstract: A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks.