Abstract: Systems and methods for reducing the amount of messages transmitted in large-scale distributed mesh networks are disclosed. Network components include transceivers and memory storing instructions which, when executed by a processing unit, reduce transmissions made by the transceiver within the network. The instructions executed by processing unit could (1) create an expiration parameter to limit the number of times a signal is retransmitted, (2) form groups of network components from which one or a few of the group network components are designated to respond on behalf of the group, (3) keep advertising transmissions dormant by default until called upon, (4) employ a time delay parameter for a time interval in which no transmission may be made, and (5) include message IDs in control signals that are transmitted.

Abstract: A blender system that includes a base that is select ively and operatively engaged with a container is shown and described herein. The base may include a near field communications chip that may communicate with a near field communications chip of a container. The base also includes a motor that is selectively and operatively engaged with a blade disposed within the container.

Abstract: A system including a valve. The valve includes a valve body having an interior volume and a bore along a first axis. A stem extends along a second axis and a flow control element couples to the stem. The stem selectively moves the flow control element through the interior volume between a closed position and an open position relative to the bore. A valve insert system retains a pressurized lubricant in the interior volume.

Abstract: A shield around an x-ray tube, a voltage multiplier, or both can improve the manufacturing process by allowing testing earlier in the process and by providing a holder for liquid potting material. The shield can also improve voltage standoff. A shielded x-ray tube can be electrically coupled to a shielded power supply.

Abstract: An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The dielectric layer may be a low-stress layer that imparts no stress or less stress than a failure stress of fragile material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with another opposing interconnect at a low-temperature below the thermal degradation temperature of thermally-sensitive material in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) that is greater than a CTE of the dielectric layer to facilitate 3D-integration.

Abstract: A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

Abstract: A pitch-yaw actuation system includes a pitch frame, a yaw frame, a pitch actuator, a yaw actuator, and a universal joint assembly. The pitch frame is pivotably coupled to a device frame via a pitch hinge. The yaw frame is pivotably coupled to the pitch frame via a yaw hinge. The pitch actuator pivots the pitch frame about a pitch axis. The yaw actuator pivots the yaw frame about a yaw axis oriented orthogonal to the pitch axis. The universal joint assembly couples the yaw actuator to the yaw frame, and includes a universal joint slidably coupled to a linear guide mechanism. The guide mechanism axis is oriented at an angle that allows the universal joint to move in a manner accommodating misalignment of the yaw actuator with the yaw frame during pivoting of at least one of the pitch frame and the yaw frame.

Abstract: A device actuation system for actuating a treatment device includes a first drive gear rotatably mountable to the treatment device, a coupler rail slidably mountable to the treatment device, a second drive gear rotatably mountable to the coupler rail, and a coupler gear rotatably mountable to the treatment device and engageable with the coupler rail. In addition, the device actuation system includes a drive rail locatable between the first drive gear and the second drive gear of the gear system. The coupler gear is rotatable to move the coupler rail in a manner maintaining the second drive gear in continuous engagement with the drive rail against the first drive gear. The first drive gear and the second drive gear are rotatable in a manner causing at least one of translation and rotation of the treatment device relative to the drive rail.

Abstract: Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.

Abstract: An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

Abstract: Disclosed are acyclic nucleoside prodrugs with improved metabolic stability and oral bioavailability. In general, the prodrugs are derivatives of acyclic nucleoside phosphonates containing a lipid-like moiety that can increase oral absorption and subsequent stability in the liver and plasma. Preferably, the lipid-like moiety can resist enzyme-mediated ?-oxidation, such as ?-oxidation catalyzed by cytochrome P450 enzymes. Also disclosed are pharmaceutical formulations of the acyclic nucleoside prodrugs. The acyclic nucleoside prodrugs and pharmaceutical formulations thereof can be used to treat viral infections, such as HIV infections, and/or viral-associated cancer, such as HPV-associated cancers.

Abstract: A blender system that includes a base that is selectively and operatively engaged with a container is shown and described herein. The base may include a near field communications chip that may communicate with a near field communications chip of a container. The base also includes a motor that is selectively and operatively engaged with a blade disposed within the container.

Abstract: A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.

Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first, via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.

Abstract: A planar filament 11f can include multiple materials to increase electron emission in desired directions and to suppress electron emission in undesired directions. The filament 11f can include a core-material CM between a top-material TM and a bottom-material BM. The top-material TM can have a lowest work function WFt; the bottom-material BM can have a highest work function WFb; and the core-material CM can have an intermediate work function WFc(WFt<WFc<WFb). A width Wt of the filament 11f at a top-side 31t can be greater than its width Wb at a bottom-side 31b (Wt>Wb). This shape makes it easier to coat the edges 31e with the bottom-material BM, because the edges 31e tilt toward and partially face the sputter target. This shape also helps direct more electrons to a center of the target 14, and reduce electron emission in undesired directions.

Abstract: Apparatus and associated methods relate to automatically load matching, in time, energy physically generated and transmitted to a consumption location across at least one tracking and processing infrastructure. In an illustrative example, a load pool (LP) may be created based on energy consumed at a physical location at one or more selected time periods. A generation pool (GP) may, for example, be created based on energy generated and physically available for consumption at the physical location during the time periods. Associations may be created, for example, between measurements in the GP of energy generated and transmitted and measurements in the LP of energy consumed. The associations may be created as a function of predetermined privileges associated with the consumption location and generation locations and/or physical transmission links corresponding to the GP during the time periods. Various embodiments may advantageously determine environmental impact based on location and time-based load matching.

Abstract: A target for an x-ray tube can emit x-rays in response to impinging electrons. Some electrons rebound without interacting atomically to form x-rays. Problems of these non-interacting electrons include reduced x-ray flux, charging electrically-insulative components of the x-ray tube, and misdirecting the electron beam. The target can include an array of holes, an array of posts, or both. The holes/posts can increase electron interaction with material of the target. Consequently, a higher percentage of impinging electrons can form x-rays. The holes/posts can also allow the target to effectively generate x-rays of different energies by providing a target with multiple thicknesses. X-rays can be generated in thicker regions of the target with the x-ray tube operated at a larger voltage. X-rays can be generated in thinner regions of the target with the x-ray tube operated at a smaller voltage.

Abstract: An integrated circuit assembly including a first wafer bonded to a second wafer with an oxide layer, wherein a first surface of the first wafer is bonded to a first surface of the second wafer. The assembly can include a bonding oxide on a second surface of the second wafer, wherein a surface of the bonding oxide is polished. The assembly can further include a shim secured to the bonding oxide on the second surface of the second wafer to reduce bow of the circuit assembly.