Abstract: A load supply voltage regulator assembly including a regulation loop containing a differential amplifier (12) whose input (28) receives a signal as a function of the load supply voltage and whose output (50) furnishes a regulation signal as a function of the deviation of the supply voltage from a nominal value as a regulation variable prompting a controlled system (56) in said regulation loop to eliminate the deviation of the supply voltage from the nominal value. The gain of the differential amplifier (12) can be switched from a low to a high value when the supply voltage changes to values violating a predefined nominal voltage range due to a change in the current requirement of the load (58).

Abstract: A loss-of-ground protection circuit for an electronic relay including a control circuit driving a power transistor, and at least one cutoff transistor having a grounded control terminal, the cutoff transistor being interposed between the control circuit and a control terminal of the power transistor, and having a polarity such that loss of ground will cause the cutoff transistor to turn off.

Abstract: The invention relates to a DC/DC converter operating on the charge pump principle, regulated to a fixed, predetermined output voltage and comprising two charge pump capacitors switched in a switch matrix consisting of nine switches. A control circuit is provided capable of controlling the switches so that the charge pump is changed over between a charging phase and a discharge phase and which is capable of operating the charge pump in two modes having different voltage gain factors (1.5; 2).

Abstract: The invention relates to a DC/DC converter operating on the principle of a charge pump and comprising a first capacitor C1 alternatingly charged via four MOSFETs M1-M4 to the input voltage and then discharged in series with the input voltage via a second capacitor C2 connected to the output of the circuit. To set the starting current for charging the as yet empty capacitors to a precisely defined small value a switchable current mirror M3, M5 is used comprising one of the four MOSFETs (M3) and a further small MOSFET (M5) which is connected to a current source 4. A comparator 5 handles selection between the starting phase and the normal charge pump mode by comparing the output voltage Vout of the converter to a reference voltage Vref, it switching the current mirror and—via two small switches S2 and S3 connected to the gates of two of the four MOSFETs—also two of the four MOSFETs so that the capacitors may be charged in an energy-saving way.

Abstract: A CMOS circuit (10), which is integrated in a semiconductor substrate, comprises a principal circuit part (12), which includes the major part of the circuit components in a well isolated from the substrate by a substrate diode. The CMOS circuit furthermore comprises a power output stage (16) driving an inductive load (26, 28). A sensor (18) is connected with one output (22, 24) of the power output stage (16) and on detection of a voltage biasing the substrate diode (30, 32) in the conducting direction produces a switching signal at the output. On occurrence of the switching signal produced by the sensor (18) a controllable switch (20) disconnects the supply voltage from the principal circuit part (12). In its own separate well (46) a status memory (14) is formed on the substrate adjacent to the principal circuit part (12), such status memory (14) comprising memory elements for storage of status data of the principal circuit part (12) on disconnection of the supply voltage.

Abstract: A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

Abstract: The invention relates to a circuit arrangement for testing the operation of a current monitoring circuit for a power transistor. The power transistor consists of several single transistors of the same size connected in parallel, through which a fraction of the total current supplied to the power transistor flows. A monitoring signal proportional to the current flowing through one of the single transistors, is supplied to the current monitoring circuit, which generates an alarm signal when this monitoring signal exceeds a specified threshold value. The single transistors are divided into a group containing a small number of single transistors (T.sub.1.1 -T.sub.1.9) connected in parallel and a group with a larger number of single transistors (T.sub.2.1,1 -T.sub.2.2,9) connected in parallel, which can be driven independently of each other, where the single transistor (T.sub.S) supplying the monitoring signal belongs to the smaller group.

Abstract: A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

Abstract: A circuit arrangement 10 for driving an MOS field-effect transistor QO allocated to the supply circuit KO of an electrical load R.sub.L contains a charging circuit K1 and a discharging circuit K2, which can be alternatively connected to the MOS field-effect transistor QO. A sensing circuit K3 supplies the measuring signal S.sub.M typical of gate-source voltage U.sub.GS of the MOS field-effect transistor QO, via which the internal resistance of the charging or discharging circuit K1, K2 and/or a current I.sub.a impressed upon these circuits K1, K2, in the sense of a positive feedback, is controlled, in such a way that the resulting time constant, according to which the input capacitance of the MOS field-effect, transistor QO is charged or discharged, becomes smaller during the transition of the MOS field-effect transistor QO from the off state to the conductive state and larger during the transition from the conductive to the off-state.

Abstract: The phase grating of the present invention includes a substrate with a reflective, continuous layer disposed thereon on which a structured spacer layer 3 of dielectric material is applied. To form a phase grating that can be used as a scale in photoelectric position measuring instruments, a further thin reflective surface layer is located solely on the reflective, continuous surfaces, parallel to the layer, of the structured spacer layer.

Abstract: An edge detector for producing output signals in a manner dependent on positive and/or negative edges of an input signal comprises a control circuit (10), by which a reference signal level (V.sub.ref) available at a storage element (C) may be continuously assimilated at a predeterminable first level change rate (PG.sub.1) to the input voltage level (V.sub.E). It moreover includes at least one comparison circuit (12), which supplies an output signal (V.sub.A, V.sub.A ') indicative of the occurrence of an edge, when the input voltage level (V.sub.E) changes by at least a predeterminable relative threshold value (U.sub.off) in relation to the reference voltage level (V.sub.ref). The control circuit (10) comprises a delay means (14) whose delay time (.DELTA.t.sub.D) causing a delay in the assimilation of the reference voltage level is selected to be equal to the ratio of the predeterminable relative threshold value (U.sub.off) to the predeterminable first level change rate (PG.sub.1).

Abstract: A circuit arrangement for gate-controlling a MOS field-effect transistor (T.sub.o) comprises a discharge circuit (12) via which the charge stored in the gate-source capacitance (C.sub.GS) can be discharged according to a time constant, the value of which depends on the internal impedance of said discharge circuit (12). This discharge circuit (12) can be switched between two conditions determined by a relatively large and a relatively small internal impedance respectively and assumes the condition dictated by the relatively small internal impedance as soon as the gate-source voltage (U.sub.GS) has dropped below a predetermined limit.

Abstract: An output circuit includes a power MOSFET with a gate connected to a plurality of diodes, the plurality of diodes forming a diode string. A resistor is connected in parallel with the diode string. A switch is connected between the opposite end of the diode string and circuit ground. A control terminal of the switch is connected to the circuit input and determines whether the circuit is turned on or turned off. An inductive load is connected to a drain terminal of the power MOSFET. The opposite end of the inductive load is connected to a power supply. A source terminal of the power MOSFET is connected to circuit ground thus providing a low-side driver circuit configuration. The resistor and diode string, connected in parallel, along with the switch provide a two-phase, soft turn-off mechanism which allows the power MOSFET to dissipate the energy stored in the inductive load without the power MOSFET entering breakdown, therefore improving the circuit's reliability.

Abstract: A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).

Abstract: The present invention relates to a voltage multiplier for generating an output voltage which is several times greater than the operating voltage for connection of a load connected to ground to the operating voltage by means of an N-channel power MOS transistor, comprising a plurality of capacitors (C1, C2, C3), a control input (C) for supplying a control signal, an output (V.sub.out), an operating voltage terminal (Vb) and a ground terminal (M). In known voltage multipliers, for rectification and multiplication of the output voltage diodes are used which reduce the maximum output voltage obtainable and restrict the clock frequency of the control signal to a few hundred kHz.

Abstract: The present invention relates to a switchable MOS current mirror having an input and an output current branch (1, 2), a plurality of first and second MOS-field-effect transistors, and a circuit section containing a third and a fourth MOS field effect transistor (Q3, Q4). The gate electrodes of the first MOS field-effect transistors are connected respectively to a gate electrode of a second MOS field-effect transistor and to the respective drain electrodes of the first MOS field-effect transistors. The gate electrode of the third and the gate electrode of the fourth MOS field-effect transistor are connected to a control terminal (S) and to the operating voltage (Vb) respectively.

Abstract: A recording medium with a multicolor high resolution pattern created by layer packs. Pattern-forming layers of the layer packs are successively applied by photolithographic means in a sequence corresponding to a color of the high resolution pattern. The pattern-forming layers of the layer packs are separate from one another on the substrate of the recording medium.The process for producing the recording medium includes applying a photoresist layer to a substrate and developing the photoresist. Pattern-forming layers are successively applied over the whole surface of the substrate in a sequence corresponding to a color. The remaining photoresist and the layers overlying it are removed to leave a sequence of pattern-forming layers on the substrate separate from any adjacent pattern-forming layers.

Abstract: A process for photolithographically producing matt diffusion patterns is disclosed. The matt diffusion patterns can be formed along with opaque and transparent patterns on the same pattern carrier plate. According to this process, a photoexposure mask corresponding to the desired matt pattern is made by photolithography, which mask is then used in subsequent photolithographic processes to form the matt diffusion pattern on pattern carrier plates. The process of making the exposure mask involves forming a mask of a desired diffusion pattern, applying a photoresist layer to the mask, exposing the photoresist layer through a diffusion plate, developing the photoresist layer, applying an opaque layer to the mask, and removing the photoresist layer. In subsequent photolithographic processes the exposure mask is printed on transparent pattern carrier plates, and the exposed areas of the pattern carrier plates are deeply etched to form the matt diffusion patterns.

Abstract: A process for forming a high resolution recording medium including at least a high resolution, patterned interference filter formed from at least two reflecting layers separated by an interference layer including the step of removing patterned portions of a reflective layer not protected by a photosensitive layer by means of chemical etching or ion beam etching. When chemical etching is used, the etching process is accelerated to reduce under-etching by maintaining a rapid, thorough, and continuous boundary surface exchange of the etching solution at the boundary between the etching solution and the reflective layer being etched.