Patents by Inventor Errol Sanchez
Errol Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180261454Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.Type: ApplicationFiled: June 27, 2016Publication date: September 13, 2018Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
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Patent number: 9570328Abstract: Apparatus for use with multi-zonal heating sources are provided. In some embodiments, a substrate support may have a pocket disposed in a surface of the substrate support and a lip disposed about the pocket to receive an edge of a substrate and to support the substrate over the pocket such that a gap is defined between a pocket surface and a backside surface of the substrate when the substrate is disposed on the lip; a plurality of features to operate in combination with a plurality of heating zones provided by a multi-zonal heating source to provide a desired temperature profile on a frontside surface of a substrate when the substrate is disposed on the lip, and wherein the plurality of features are alternatingly disposed above and below a baseline surface profile of the pocket surface in a radial direction from a central axis of the substrate support.Type: GrantFiled: June 8, 2011Date of Patent: February 14, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Kailash Patalay, Errol Sanchez
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Publication number: 20170004968Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.Type: ApplicationFiled: June 27, 2016Publication date: January 5, 2017Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
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Patent number: 9058988Abstract: Methods of depositing layers having reduced interfacial contamination are disclosed herein. The inventive methods may advantageously reduce contamination at the interface between deposited layers, for example, between a deposited layer and an underlying substrate or film. In some embodiments, a method of depositing a layer may include annealing a silicon-containing layer having a first layer disposed thereon in a reducing atmosphere; removing the first layer using an etching process to expose the silicon-containing layer after annealing; and depositing a second layer on the exposed silicon-containing layer.Type: GrantFiled: March 4, 2010Date of Patent: June 16, 2015Assignee: APPLIED MATERIALS, INC.Inventors: Jean R. Vatus, Jinsong Tang, Yihwan Kim, Satheesh Kuppurao, Errol Sanchez
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Patent number: 8999821Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.Type: GrantFiled: May 5, 2014Date of Patent: April 7, 2015Assignee: Applied Materials, Inc.Inventors: Adam Brand, Bingxi Wood, Errol Sanchez, Yihwan Kim, Yi-Chiau Huang, John Boland
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Patent number: 8991332Abstract: Systems and apparatus are disclosed for adjusting the temperature of at least a portion of the surface of a reaction chamber during a film formation process to control film properties. More than one portion of the chamber surface may be temperature-modulated.Type: GrantFiled: February 27, 2009Date of Patent: March 31, 2015Assignee: Applied Materials, Inc.Inventors: Satheesh Kuppurao, David K. Carlson, Manish Hemkar, Andrew Lam, Errol Sanchez, Howard Beckford
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Publication number: 20150050800Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.Type: ApplicationFiled: May 5, 2014Publication date: February 19, 2015Inventors: Adam Brand, Bingxi Wood, Errol Sanchez, Yihwan Kim, Yi-Chiau Huang, John Boland
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Patent number: 8524555Abstract: Methods and apparatus for providing constant emissivity of the backside of susceptors are described. Provided is a method comprising: providing a susceptor in a deposition chamber, the susceptor comprising a susceptor plate and a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof, the layer being stable in the presence of the reactive process gases; and locating the wafer on a support surface of the susceptor plate. The method can further comprise selectively depositing an epitaxial layer or a non-epitaxial layer on a surface of the wafer. The method can also further comprise selectively etching to maintain the oxide, nitride, oxynitride, or combinations thereof layer.Type: GrantFiled: June 22, 2012Date of Patent: September 3, 2013Assignee: Applied Materials, Inc.Inventors: Errol Sanchez, David K. Carlson, Craig Metzner
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Patent number: 8501600Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.Type: GrantFiled: July 25, 2011Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Errol Sanchez, Yi-Chiau Huang, David K. Carlson
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Patent number: 8501594Abstract: Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H2SiCl2), trichlorosilane (HSiCl3), or silicon tetrachloride (SiCl4). In some embodiments, the second silicon precursor gas may comprise at least one of silane (SiH4), or disilane (Si2H6).Type: GrantFiled: June 15, 2010Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Yi-Chiau Huang, Masato Ishii, Errol Sanchez
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Patent number: 8313804Abstract: Methods and apparatus are disclosed for the formation of vaporizing liquid precursor materials. The methods or apparatus can be used as part of a chemical vapor deposition apparatus or system, for example for forming films on substrates. The methods and apparatus involve providing a vessel for containing a liquid precursor and diffusing element having external cross-section dimensions substantially equal to the internal cross-sectional dimensions of the vessel.Type: GrantFiled: May 17, 2011Date of Patent: November 20, 2012Assignee: Applied Materials, Inc.Inventors: David K. Carlson, Errol Sanchez, Satheesh Kuppurao
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Publication number: 20120282714Abstract: Methods and apparatus for providing constant emissivity of the backside of susceptors are described. Provided is a method comprising: providing a susceptor in a deposition chamber, the susceptor comprising a susceptor plate and a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof, the layer being stable in the presence of the reactive process gases; and locating the wafer on a support surface of the susceptor plate. The method can further comprise selectively depositing an epitaxial layer or a non-epitaxial layer on a surface of the wafer. The method can also further comprise selectively etching to maintain the oxide, nitride, oxynitride, or combinations thereof layer.Type: ApplicationFiled: June 22, 2012Publication date: November 8, 2012Applicant: Applied Materials, Inc.Inventors: Errol Sanchez, David K. Carlson, Craig Metzner
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Patent number: 8226770Abstract: Methods and apparatus for providing constant emissivity of the backside of susceptors are provided. Provided is a susceptor comprising: a susceptor plate having a surface for supporting a wafer and a backside surface opposite the wafer supporting surface; a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof located on the backside surface of the susceptor plate, the layer being stable in the presence of a reactive process gas. The layer comprises, for example, silicon dioxide, silicon nitride, silicon oxynitride, or combinations thereof. Also provided is a method comprising: providing a susceptor in a deposition chamber, the susceptor comprising a susceptor plate and a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof, the layer being stable in the presence of the reactive process gases; locating the wafer on a support surface of the susceptor plate.Type: GrantFiled: May 4, 2007Date of Patent: July 24, 2012Assignee: Applied Materials, Inc.Inventors: Errol Sanchez, David K. Carlson, Craig Metzner
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Publication number: 20120077335Abstract: Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements.Type: ApplicationFiled: July 25, 2011Publication date: March 29, 2012Applicant: APPLIED MATERIALS, INC.Inventors: ERROL SANCHEZ, YI-CHIAU HUANG, DAVID K. CARLSON
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Publication number: 20120003599Abstract: Apparatus for use with multi-zonal heating sources are provided. In some embodiments, a substrate support may have a pocket disposed in a surface of the substrate support and a lip disposed about the pocket to receive an edge of a substrate and to support the substrate over the pocket such that a gap is defined between a pocket surface and a backside surface of the substrate when the substrate is disposed on the lip; a plurality of features to operate in combination with a plurality of heating zones provided by a multi-zonal heating source to provide a desired temperature profile on a frontside surface of a substrate when the substrate is disposed on the lip, and wherein the plurality of features are alternatingly disposed above and below a baseline surface profile of the pocket surface in a radial direction from a central axis of the substrate support.Type: ApplicationFiled: June 8, 2011Publication date: January 5, 2012Applicant: APPLIED MATERIALS, INC.Inventors: KAILASH PATALAY, ERROL SANCHEZ
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Publication number: 20110155058Abstract: Methods and apparatus for processing substrates are disclosed herein. In some embodiments, an apparatus for processing a substrate may include a substrate support having a base having a convex surface, an annular ring disposed on the base, and an edge ring disposed on the annular ring to support a substrate, wherein the base, annular ring, and edge ring form a radiant cavity capable of reflecting energy radiated from a backside of a substrate when disposed on the edge ring and wherein the backside of the substrate faces the convex surface of the base. Alternatively or in combination, in some embodiments, the base may include a metal layer encapsulated between a transparent non-metal upper layer and a non-metal lower layer.Type: ApplicationFiled: December 14, 2010Publication date: June 30, 2011Applicant: APPLIED MATERIALS, INC.Inventors: David K. Carlson, Errol Sanchez, Herman Diniz, Satheesh Kuppurao
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Publication number: 20100317177Abstract: Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H2SiCl2), trichlorosilane (HSiCl3), or silicon tetrachloride (SiCl4). In some embodiments, the second silicon precursor gas may comprise at least one of silane (SiH4), or disilane (Si2H6).Type: ApplicationFiled: June 15, 2010Publication date: December 16, 2010Applicant: APPLIED MATERIALS, INC.Inventors: YI-CHIAU HUANG, MASATO ISHII, ERROL SANCHEZ
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Patent number: 7838431Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate having at least one of a defect or a contaminant disposed on or near a surface of the substrate; and selectively annealing a portion of the substrate with a laser beam in the presence of a process gas comprising hydrogen. The laser beam may be moved over the substrate or continuously, or in a stepwise fashion. The laser beam may be applied in a continuous wave or pulsed mode. The process gas may further comprise an inert gas, such as, at least one of helium, argon, or nitrogen. A layer of material may be subsequently deposited atop the annealed substrate.Type: GrantFiled: June 20, 2008Date of Patent: November 23, 2010Assignee: Applied Materials, Inc.Inventor: Errol Sanchez
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Publication number: 20100255661Abstract: Methods of depositing layers having reduced interfacial contamination are disclosed herein. The inventive methods may advantageously reduce contamination at the interface between deposited layers, for example, between a deposited layer and an underlying substrate or film. In some embodiments, a method of depositing a layer may include annealing a silicon-containing layer having a first layer disposed thereon in a reducing atmosphere; removing the first layer using an etching process to expose the silicon-containing layer after annealing; and depositing a second layer on the exposed silicon-containing layer.Type: ApplicationFiled: March 4, 2010Publication date: October 7, 2010Applicant: APPLIED MATERIALS, INC.Inventors: JEAN R. VATUS, JINSONG TANG, YIHWAN KIM, SATHEESH KUPPURAO, ERROL SANCHEZ
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Patent number: 7737007Abstract: In one embodiment, a method for forming a silicon-based material on a substrate having dielectric materials and source/drain regions thereon within a process chamber is provided which includes exposing the substrate to a first process gas comprising silane, methylsilane, a first etchant, and hydrogen gas to deposit a first silicon-containing layer thereon. The first silicon-containing layer may be selectively deposited on the source/drain regions of the substrate while the first silicon-containing layer may be etched away on the surface of the dielectric materials of the substrate. Subsequently, the process further provides exposing the substrate to a second process gas comprising dichlorosilane and a second etchant to deposit a second silicon-containing layer selectively over the surface of the first silicon-containing layer on the substrate.Type: GrantFiled: August 29, 2008Date of Patent: June 15, 2010Assignee: Applied Materials, Inc.Inventors: Arkadii V. Samoilov, Yihwan Kim, Errol Sanchez, Nicholas C. Dalida