Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.

Abstract: An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device.

Abstract: A method of fabricating a semiconductor device (200) is described. According to a described embodiment, the method comprises: (i) forming a 111-V semiconductor material layer (206) comprising a substrate layer (208) and a device layer (210) attached to the substrate layer (208); and (ii) forming an electrically conductive interlayer (228) to the device layer (210) prior to bonding the electrically conductive interlayer (228) to a partially processed CMOS device layer (204) having at least one transistor (205).

Abstract: An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device. The method comprises the steps of providing a complementary metal-oxide-semiconductor, CMOS, backplane comprising a driver circuit for the optoelectronic device; and providing a plurality of optical elements on the CMOS backplane, wherein the plurality of optical elements are based on a material system different from CMOS and are disposed in different device layers; wherein a first bonding dielectric is provided between the CMOS backplane and a first one of the different device layers for monolithic integration; and wherein a second bonding dielectric is provided between respective ones of the different device layers for monolithic integration, the second bonding dielectric being transparent.

Abstract: An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

Abstract: An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

Abstract: Disclosed is a method of reducing surface unevenness of a semiconductor wafer (100). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (1123). In the described embodiment, the deposited layer includes an epitaxial layer (112) and the protective layer includes a first dielectric layer (113). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (112). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.

Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.

Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.

Abstract: A multi-junction solar cell includes a plurality of photovoltaic cell layers that are electrically connected and stacked to define upper and lower subcells having at least one step difference therebetween that exposes portions of the lower subcell such that, responsive to incident illumination, a current density of the exposed portions of the lower subcell is greater than that of portions thereof having the upper subcell thereon. Related devices and fabrication methods are also discussed.

Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.

Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.

Abstract: A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.

Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Abstract: A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.

Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.