Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a strain-inducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.

Abstract: Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a first in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer.

Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.

Abstract: Solar cells include a substrate consisting essentially of silicon, a first junction disposed over the substrate, the first junction comprising at least one III-V material and having a threading dislocation density of less than approximately 107 cm?2, and a cap layer disposed over the first junction, the cap layer comprising silicon.

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer.

Abstract: A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.

Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.

Abstract: A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based photodetector comprising an active region including at least a portion of the monocrystalline silicon layer.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes one or more III-IV material-based semiconductor layers. A tensile-strained Ge layer is formed on the one or more a III-IV material-based semiconductor layers. The tensile-strained Ge layer is produced through lattice-mismatched heteroepitaxy on the one or more a III-IV material-based semiconductor layers.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.