Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.

Abstract: An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.

Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.

Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.

Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.

Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used.

Abstract: A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract: Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.