PACKAGING OF HIGH PERFORMANCE SYSTEM TOPOLOGY FOR NAND MEMORY SYSTEMS
A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.
This application is a continuation of U.S. application Ser. No. 13/904,770, filed on May 29, 2013, the entirety of which is incorporated by reference herein.
FIELD OF THE INVENTIONThis invention pertains generally to the field of non-volatile memory and, more particularly, to the topology of the memory chips within such systems.
BACKGROUNDNon-volatile memory systems, such as those formed from NAND flash memory chips, typically include one or more controller chips connected to multiple memory chips. In some cases, such as in solid state drives (SSDs), the number of memory chips can be quite large. For example, with a NAND density of 128 Gb, or 16 GB, a 8 TB SSD drive with 100% over-provision (redundancy) would have 1024 NAND chips. If the system has 16 input/output (IO) channels, each channel has 64 NAND chips. The capacitive pin loading load of NAND chips impose limitations on system clock operation frequency to ensure signal integrity as the drivers may not be able to handle the cumulative load. Because of this, it is a challenge to push data transfer rates to higher frequencies.
SUMMARY OF THE INVENTIONAccording to a first set of general aspects, a non-volatile memory system includes a memory section having a plurality of non-volatile memory circuits and a bus structure. In the memory section, each of the memory circuits includes an array of non-volatile memory cells and a latch circuit, where the latch circuit is connectable to a bus input to receive data and commands therefrom and to a bus output to provide data and responses. In response to commands received on bus input the memory circuit can operate in a plurality of modes including: a pass-through mode, where the memory array is inactive and commands and data are passed by the latch circuit from the bus input to the bus output; and an active mode, in which the memory array is active and data can be transferred between the memory array and the bus input or bus output by the latch circuit. The bus structure connects the bus inputs and bus outputs of the non-volatile memory circuits for the transfer of data and commands. The bus structure includes an input bus for the memory section connected to the bus input of a first of the memory circuits, an output bus for the memory section connected to the bus output of a second of the memory circuit, and first and second intermediate busses. The first intermediate bus connects the bus output of the first memory circuit to the bus inputs of a first set of multiple other ones of the memory circuits, the first set not including the second memory circuit. The second intermediate bus connects the bus input of the second memory circuit to the bus outputs of a second set of multiple other ones of the memory circuits, the second set not including the first memory circuit.
Further aspects relate to a non-volatile memory system with a memory section having multiple non-volatile memory circuits. Each of the memory circuits includes an array of non-volatile memory cells and a latch circuit, where the latch circuit is connectable to a first input-output port to receive data and commands and provide data therefrom and to a second input-output port to provide data and commands and receive data therefrom. In response to commands received on the first input-output port the memory circuit can operate in a plurality of modes including: pass-through modes, wherein the memory array is inactive and commands and data are passed by the latch circuit from the first input-output port to the second input-output port or from the second input-output port to the first input output port; and active modes, in which the memory array is active and data can be transferred between the memory array and the first input-output port by the latch circuit. The memory section also has a bus structure connecting the first input-output ports and second input-output ports of the non-volatile memory circuits for the transfer of data and commands. The bus structure includes an initial bus segment for the memory section connected to the first input-output port of a first of the memory circuits and a first intermediate bus segment connecting the second input-output port of the first memory circuit to the first input-output ports of a first set of multiple other ones of the memory circuits.
Other aspects relate to a non-volatile memory integrated circuit having a plurality of external contact pads, primary circuitry portion, and a switching circuit. The external contact pads include a first set of a plurality of N external contact pads and a second set of N external contact pads. The primary circuitry portion includes a non-volatile memory array and associated peripheral circuitry and has, when operating in a first mode, N input lines and N output lines. The switching circuit is connected to the first and second sets of external contact pads connected to the input and output lines. The switching circuit can selectively attach the first and second sets of external contact pads to the input and output lines in either a first configuration, where the N input lines are attached to the first set of external contact pads and the N output lines are attached to the second set of external contact pads, or in a second configuration, where the N input lines are attached to the second set of external contact pads and the N output lines are attached to the first set of external contact pads.
Additional aspect concern a non-volatile memory package having multiple external bonding pads formed thereupon, the external bonding pads including a plurality of external input pads and a plurality of external output pads. The package contains multiple non-volatile memory chips each having a first set and a second set of N contact pins where each of the memory chips can be individually configured to operate in either a first configuration, where the first set of pins are input pins and the second set of pins are output pins, and a second configuration, where the first set of pins are output pins and the second set of pins are input pins. The memory chips include a first memory chip connected with the input pins thereof connected to the external input pads, a second memory chip connected with the output pins thereof connected to the external output pads, and one or more additional memory chips, where, aside from the input pins of the first memory chip and the output pins of the second memory chip, the first, second and additional memory chips are connected so that the output pins of each memory chip are connected to the input pins of one or more other memory chips and the input pins of each memory chip are connected to the output pins of one or more other memory chips. The memory chips are stacked with chips configured according to the first configuration interleaved with chips configured according to the second configuration.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, whose description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
As discussed in the Background, non-volatile memory systems having large numbers of memory chips, such as a NAND based solid state drive (SSD) can suffer from large amount of capacitive loading on pins of the memory chips, limiting transfer rates. The following addresses this problem by introducing a topology for the memory chips that can significantly reduce the capacitive loading, allowing for much higher IO data transfer rates.
In a first set of aspects, the memory chip includes a new alternate or additional interface relative to the chip's existing interface. This interface can be controlled by an internal ROM fuse, for example. This new interface can also help to the overloading of pins with features that are found on convention interfaces. This additional interface is illustrated with respect to
The memory chip 15 can operate in an active mode and a pass-through mode, with it typically useful to also have a stand-by mode. These modes are illustrated schematically in
In the pass through mode, illustrated in
The ability of the interface based on the DFF 19 to pass commands, addresses and data from the input bus 13 to the output bus 21 allows for the memory chips to be connected according to a topology that can significantly reduce the amount of capacitive loading on the pins. This is described with respect to
The output data lines 105 from 101 at DO are then connected to the data input DI at each of the (in this example) four chips 121, 123, 125, 127 of the second tier. Similarly, the output clock from CKO of 101 is supplied along 105 to the clock input CKI of each of the second tier chips. This process is then repeated at tier 3, where each of the tier 2 chips are connected to drive a number (four again, in this example) of chips, where only the chips 141, 143, 145, 147 being fed by chip 121 are shown to simplify the diagram for purposes of discussion. The data out lines of chip 121 are connected over 135 to the data input pins of each of 141, 143, 145, 147, with the clock signal transferred from CKO of 121 over line 133 to the CKI pin of each of 141, 143, 145, 147. Under this arrangement, each device only drives four chips at most, relative to the arrangement of
In the exemplary arrangement of
The memory section of
Within the package, the input and output pad sets can be swapped from chip to chip to more efficiently implement the topology. This can shorten and simplify the connections between the outputs of one tier with the inputs of the following tier. One exemplary embodiment for the 10 die package of
As noted,
Both in
As noted above, in the exemplary embodiment the memory chip can be operated in one mode with the pins assigned as developed above, with a number of pins being set aside as input bus lines and a similar number set aside as output bus lines, or in mode using a standard interface, as in
For any of these arrangements, as the signals travel through the branches to the different chips of the tree, the signals should preferably maintain a degree of synchronization. The re-synchronization can be done through a delay-tunable clock buffer arranged such that data are resynchronized. The delay elements, which were not explicitly shown in the earlier figures, can mostly be placed at the input and/or the output of the clock buffer.
More specifically,
The inclusion of the reverse modes allows additional topologies to be used. The topologies discussed above mainly looked at the case of a tree like structure where the chips fanned out from a single initial chip, then fanned back down to a final chip and data went in one side (the chip's input bus) and out the other (output bus) as illustrated schematically as a left to right flow in the figures. With the reverse modes, the memory devices can again be structured to fan out in a tree structure, but need not fan back in, where data can be sent back out in the reverse direction to the same “trunk” device, and then out to the controller or host. This is illustrated with respect to
The top part of
For any of the embodiments discussed above, the tree like arrangement can have significant advantages over the more common arrangement illustrated with respect to
A further advantage of the tree-like relates to how defective chips can be handled. Defects will largely occur in the primary circuit portion, rather than more basic circuitry of the interface's flip-flop. If a chip is found to be defective during operation, as long as the DFF portion of the circuit can pass signals, the chips that fan out, the device can be placed into stand-by mode and mapped out. Additionally, under this arrangement, testing procedures can be simplified as the primary circuit portion need not be tested since due to the available high degree of redundancy, any chips that turn out to be defective can just be treated the same devices that fail during later operation by being put into a permanent standby mode.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
Claims
1. A non-volatile memory system comprising:
- a plurality of memory packages arranged in a memory package topology, each of the plurality of memory packages comprising a plurality of memory chips arranged in a memory chip topology, and each of the plurality of memory chips comprising: a plurality of memory cells; a first input-output port; a second input-output port; and a latch circuit having a first port connected to the first input-output port and a second port connected to the second input-output port, wherein the latch circuit is configured to transfer data and commands between the first input-output port and the second input-output port based upon a mode of operation of the plurality of memory chips on which the latch circuit is provided,
- wherein the memory package topology comprises a plurality of memory package tiers in which the plurality of memory packages are arranged, including a first memory package tier comprising a single one of the plurality of memory packages and a second memory package tier comprising multiple ones of the plurality of memory packages, wherein the single one of the plurality of memory packages in the first memory package tier is connected to each of the multiple ones of the plurality of memory packages in the second memory package tier.
2. The non-volatile memory system of claim 1, wherein each of the plurality of memory chips is configured to operate in one of the modes of operation including a stand-by mode, a forward pass-through mode, a reverse pass-through mode, a forward active mode, and a reverse active mode.
3. The non-volatile memory system of claim 2, further comprising a memory controller connected to the first input-output port of the plurality of memory chips, and wherein in the stand-by mode, the commands from the memory controller are transferred from the first input-output port to the second input-output port via the latch circuit, and the data is not transferred from the first input-output port to the second input-output port.
4. The non-volatile memory system of claim 2, further comprising a memory controller connected to the first input-output port of the plurality of memory chips, and wherein in the forward pass-through mode, the commands from the memory controller and the data are transferred from the first input-output port to the second input-output port via the latch circuit.
5. The non-volatile memory system of claim 2, further comprising a memory controller connected to the first input-output port of the plurality of memory chips, and wherein in the reverse pass-through mode, the data is transferred from the second input-output port to the first input-output port via the latch circuit, and the commands are not transferred from the second input-output port to the first input-output port, and the plurality of memory cells of the plurality of memory chips that are in the reverse pass-through mode are inactive.
6. The non-volatile memory system of claim 2, further comprising a memory controller connected to the first input-output port of the plurality of memory chips, and wherein in the active mode, the data is transferred from the first input-output port to the plurality of memory cells or from the plurality of memory cells to the first input-output port of the plurality of memory chips that are in the active mode.
7. The non-volatile memory system of claim 2, further comprising a memory controller connected to the first input-output port of the plurality of memory chips, and wherein in the reverse active mode, the data is transferred from the second input-output port to the first input-output port via the latch circuit, the commands are not transferred from the second input-output port to the first input-output port, and the plurality of memory cells of the plurality of memory chips that are in the reverse active mode are active.
8. The non-volatile memory system of claim 1, wherein the second memory package tier comprises three memory packages and the single one of the plurality of memory packages in the first memory package tier is connected to each of the three memory packages, and wherein the memory package topology further comprises a third memory package tier having one memory package, and wherein each of the three memory packages of the second memory package tier is connected to the one memory package of the third memory package tier.
9. The non-volatile memory system of claim 1, wherein the second memory package tier comprises two memory packages and the single one of the plurality of memory packages from the first memory package tier is connected to each of the two memory packages of the second memory package tier, and wherein the memory package topology further comprises:
- a third memory package tier comprising four memory packages divided into two groups of two memory packages, and each of the two memory packages of the second memory package tier is connected to one of the two groups in the third memory package tier;
- a fourth memory package tier comprising two memory packages, and each of the two groups in the third memory package tier is connected to one of the two memory packages of the fourth memory package tier; and
- a fifth memory package tier comprising one memory package, and the two memory packages of the fourth memory package tier are connected to the one memory package of the fifth memory package tier.
10. The non-volatile memory system of claim 1, wherein the memory chip topology comprises a plurality of memory chip tiers in which the plurality of memory chips are arranged, including a first memory chip tier comprising a single one of the plurality of memory chips and a second memory chip tier comprising multiple ones of the plurality of memory chips, and wherein the second input-output port of the single one of the plurality of memory chips in the first memory chip tier is connected to the first input-output port of each of the multiple ones of the plurality of memory chips in the second memory chip tier.
11. The non-volatile memory system of claim 10, further comprising a third memory chip tier having multiple groups of the plurality of memory chips, wherein a number of the plurality of memory chips in each of the multiple groups is same as a number of the multiple ones of the plurality of memory chips in the second memory chip tier, and wherein each of the multiple ones of the plurality of memory chips in the second memory chip tier is connected to the plurality of memory chips in one of the multiple groups of the third memory chip tier.
12. The non-volatile memory system of claim 11, further comprising:
- a fourth memory chip tier having a same number of the plurality of memory chips as the multiple ones of the plurality of memory chips in the second memory chip tier, and wherein each of the multiple groups of the third memory chip tier is connected to one of the plurality of memory chips in the fourth memory chip tier; and
- a fifth memory chip tier comprising one of the plurality of memory chips, and wherein each of the plurality of memory chips in the fourth memory chip tier is connected to the one of the plurality of memory chips in the fifth memory chip tier.
13. The non-volatile memory system of claim 1, wherein each of the plurality of memory chips comprises a serial data input port and a serial data output port, and wherein all of the plurality of memory chips are serially connected via the serial data input port and the serial data output port.
14. The non-volatile memory system of claim 1, further comprising a memory controller circuit connected to the single one of the plurality of memory chips of the first memory chip tier, wherein the memory controller circuit is configured to select a specified one of the plurality of memory chips for reading data from or writing data to the specified one of the plurality of memory chips.
15. A system comprising:
- a plurality of memory chips connected in a topology comprising a plurality of tiers, each of the plurality of memory chips comprising: a plurality of memory cells; a first input-output port; a second input-output port; a latch circuit having a first port connected to the first input-output port and a second port connected to the second input-output port, wherein the latch circuit is configured to facilitate communication between the first input-output port and the second input-output port based upon a mode of operation of the plurality of memory chips on which the latch circuit is provided; and
- a memory controller circuit connected to a first one of the plurality of memory chips and the first one of the plurality of memory chips is connected to other ones of the plurality of memory chips in the topology,
- wherein the memory controller circuit is configured to perform at least a read operation and a write operation on a selected one of the plurality of memory chips;
- wherein the selected one of the plurality of memory chips is operated in an active mode of operation in which data is transferred from the first input-output port to the plurality of memory cells of the selected one of the plurality of memory chips or from the plurality of memory cells to the first input-output port of the selected one of the plurality of memory chips; and
- wherein the plurality of memory chips other than the selected one of the plurality of memory chips are operated in either a stand-by mode in which commands from the memory controller circuit are transferred from the first input-output port to the second input-output port or a pass-through mode in which the commands and the data are transferred from the first input-output port to the second input-output port.
16. The system of claim 15, wherein the latch circuit is a D-flip flop.
17. The system of claim 15, wherein the plurality of tiers comprises a first tier having the first one of the plurality of memory chips, a last tier having a same number of the plurality of memory chips as the first tier, and at least one intermediary tier having multiple ones of the plurality of memory chips, and wherein in each of the at least one intermediary tier, a number of the plurality of memory chips increases from the first tier before decreasing towards the last tier.
18. The system of claim 15, wherein the plurality of memory chips is serially connected by a serial line.
19. A method comprising:
- arranging a plurality of memory chips in a topology having a plurality of tiers, wherein each of the plurality of memory chips is serially connected, and wherein each of the plurality of memory chips in each of the plurality of tiers other than a last tier is further connected to at least one of the plurality of memory chips in a next tier;
- selecting one of the plurality of memory chips for performing a read or write operation;
- placing the selected one of the plurality of memory chips in an active mode in which data is read from or written into the selected one of the plurality of memory chips;
- placing a first portion of the plurality of memory chips that provide a path between a memory controller and the selected one of the plurality of memory chips in a pass-through mode, wherein the data and commands are passed through the first portion of the plurality of memory chips in the pass-through mode; and
- placing a second portion of the plurality of memory chips in a stand-by mode, wherein the commands but not data are passed through the second portion of the memory chips.
20. The method of claim 19, further comprising transferring the commands and data through the plurality of memory circuits via a latch circuit.
Type: Application
Filed: Jul 25, 2017
Publication Date: Nov 9, 2017
Inventor: Eugene Jinglun TAM (Saratoga, CA)
Application Number: 15/659,083