Patents by Inventor Eui-Young Chung
Eui-Young Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11736308Abstract: A device for providing a location-based automatic participation chat room, the device, when a request to open a chat room is received along with service location information from at least one host terminal, creates at least one chat room, and sets a chat room identifier and a recognition code corresponding to each of the at least one chat room, and when at least one guest terminal accesses a location corresponding to the service location information using a pre-set participation means or the recognition code included in the participation means is received, makes the guest terminal participate in the chat room corresponding to the recognition code.Type: GrantFiled: September 25, 2019Date of Patent: August 22, 2023Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Eui-Young Chung, Seong-Lyun Kim, Dae Hyung Cho, Sang Hyup Lee, Gi Lee, Tae Yang Jeong
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Patent number: 11450394Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.Type: GrantFiled: August 26, 2020Date of Patent: September 20, 2022Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Soo Hong Ahn, Eui Young Chung, Young Min Park
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Publication number: 20220052864Abstract: A device for providing a location-based automatic participation chat room, the device, when a request to open a chat room is received along with service location information from at least one host terminal, creates at least one chat room, and sets a chat room identifier and a recognition code corresponding to each of the at least one chat room, and when at least one guest terminal accesses a location corresponding to the service location information using a pre-set participation means or the recognition code included in the participation means is received, makes the guest terminal participate in the chat room corresponding to the recognition code.Type: ApplicationFiled: September 25, 2019Publication date: February 17, 2022Inventors: Eui-Young CHUNG, Seong-Lyun KIM, Dae Hyung CHO, Sang Hyup LEE, Gi LEE, Tae Yang JEONG
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Patent number: 10970235Abstract: An operating method of a computing system includes storing, in a submission queue, a command entry corresponding to a request for one of input and output; fetching the command entry from the submission queue, moving data corresponding to the request within a host memory that is under control of a storage device; after moving the data, updating a completion status of the request in a completion queue; and after updating the completion queue, transferring the data between the host memory and the storage device.Type: GrantFiled: September 19, 2017Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: JuHyung Hong, Eui-Young Chung
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Publication number: 20210074373Abstract: A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.Type: ApplicationFiled: August 26, 2020Publication date: March 11, 2021Inventors: Soo Hong AHN, Eui Young CHUNG, Young Min PARK
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Patent number: 10924117Abstract: A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.Type: GrantFiled: August 6, 2019Date of Patent: February 16, 2021Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Jeongbin Kim, Kitae Kim, Kyungseon Cho, Seungjin Lee, Daehyung Cho, Eui-Young Chung, Hongil Yoon
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Publication number: 20210034286Abstract: Disclosed are a memory system for a data swap and an operating method thereof. A memory system may include a plurality of layers coupled through at least one through silicon via (TSV) channel and a swap controller configured to generate a swap control command in response to a request received from an external host and to device swap data into a plurality of data units having a predetermined size to perform a swap operation between a first layer and a second layer among the plurality of layers, wherein the first layer and the second layer include at least one swap buffer and control a movement of the plurality of data units in response to the swap control command.Type: ApplicationFiled: July 17, 2020Publication date: February 4, 2021Inventors: Eui-Young CHUNG, Sang Hyup LEE, Kwangsu KIM, Jeongbin KIM, Byoung Jin KIM
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Patent number: 10853247Abstract: Disclosed is a device for maintaining consistency between a host system cache and a main memory in a general-purpose computing system equipped with a hardware accelerator for processing main memory data. The device for maintaining data consistency between a hardware accelerator and a host system, which is at least temporarily implemented by a computer, includes a determination unit responsible for determining whether an address which the hardware accelerator should access is present in a cache, and a processing unit responsible for selectively performing write-back on data corresponding to the address when the address is present in the cache based on the determined result.Type: GrantFiled: March 17, 2017Date of Patent: December 1, 2020Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Eui Young Chung, Hyeok Jun Seo, Sang Woo Han
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Patent number: 10615801Abstract: A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.Type: GrantFiled: August 1, 2019Date of Patent: April 7, 2020Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Kangwook Jo, Jeongbin Kim, Minyoung Im, Taehee You, Eui-Young Chung, Hongil Yoon
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Patent number: 10565131Abstract: Disclosed is a main memory capable of speeding up a hardware accelerator and saving memory space. The main memory according to the present disclosure is at least temporarily implemented by a computer and includes a memory, and an accelerator responsible for performing an operation for hardware acceleration while sharing the storage space of a host processor and the memory.Type: GrantFiled: March 17, 2017Date of Patent: February 18, 2020Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Eui Young Chung, Hyeok Jun Seo, Sang Woo Han
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Patent number: 10554395Abstract: A semiconductor device may comprise a plurality of chips coupled in a ring structure, and the plurality of chips includes a first chip. Each of the plurality of chips may include a key port receiving or outputting a key to circulate the key through the ring structure. The first chip is configured to be in a standby state until an amount of available token becomes equal to or greater than an amount of required token to perform a specific operation in the first chip, when the first chip has the key.Type: GrantFiled: March 8, 2017Date of Patent: February 4, 2020Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Taehee You, Sangwoo Han, Youngmin Park, Eui-Young Chung, Jaewoo Park, Byungryul Kim, Younghwan Hong
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Patent number: 10509744Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.Type: GrantFiled: December 15, 2017Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong Ho Lee, Sung Roh Yoon, Eui Young Chung, Jin Woo Kim, Young Jin Cho, Myeong Jin Kim, Sei Joon Kim, Jeong Bin Kim, Hyeok Jun Choe
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Publication number: 20190363718Abstract: A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.Type: ApplicationFiled: August 6, 2019Publication date: November 28, 2019Inventors: Jeongbin KIM, Kitae KIM, Kyungseon CHO, Seungjin LEE, Daehyung CHO, Eui-Young CHUNG, Hongil YOON
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Publication number: 20190356316Abstract: A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Inventors: Kangwook JO, Jeongbin KIM, Minyoung IM, Taehee YOU, Eui-Young CHUNG, Hongil YOON
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Patent number: 10419000Abstract: A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.Type: GrantFiled: August 21, 2018Date of Patent: September 17, 2019Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Jeongbin Kim, Kitae Kim, Kyungseon Cho, Seungjin Lee, Daehyung Cho, Eui-Young Chung, Hongil Yoon
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Patent number: 10419001Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.Type: GrantFiled: November 2, 2017Date of Patent: September 17, 2019Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation Yonsei UniversityInventors: Kangwook Jo, Jeongbin Kim, Minyoung Im, Taehee You, Eui-Young Chung, Hongil Yoon
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Patent number: 10379585Abstract: A semiconductor device may comprise a plurality of chips coupled in a bidirectional ring structure. The plurality of chips includes a first chip, and the first chip determines whether a token is required to perform a specific operation in the first chip. The first chip further determines whether an amount of an available token in the first chip is equal to or greater than an amount of the required token to perform the specific operation. When the amount of the available token is equal to or greater than the amount of the required token, the first chip performs the specific operation and then the first chip outputs one or both of a first portion of the available token in a first direction and a second portion of the available token in a second direction. The first direction is opposite to the second direction in the bidirectional ring structure.Type: GrantFiled: March 8, 2017Date of Patent: August 13, 2019Assignee: SK HYNIX INC.Inventors: Taehee You, Sangwoo Han, Youngmin Park, Eui-Young Chung, Jaewoo Park, Byungryul Kim, Younghwan Hong
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Publication number: 20190199353Abstract: A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.Type: ApplicationFiled: August 21, 2018Publication date: June 27, 2019Inventors: Jeongbin Kim, Kitae Kim, Kyungseon Cho, Seungjin Lee, Daehyung Cho, Eui-Young Chung, Hongil Yoon
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Publication number: 20180287614Abstract: A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.Type: ApplicationFiled: November 2, 2017Publication date: October 4, 2018Inventors: Kangwook JO, Jeongbin KIM, Minyoung IM, Taehee YOU, Eui-Young CHUNG, Hongil YOON
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Publication number: 20180189206Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.Type: ApplicationFiled: December 15, 2017Publication date: July 5, 2018Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: JEONG HO LEE, SUNG ROH YOON, EUI YOUNG CHUNG, JIN WOO KIM, YOUNG JIN CHO, MYEONG JIN KIM, SEI JOON KIM, JEONG BIN KIM, HYEOK JUN CHOE