Abstract: Cooled electronic assemblies and methods of fabrication are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic component(s), and one or more coolant-carrying channel(s) integrated within the module, and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure facilitates flow of coolant to the coolant-carrying channel(s) of the electronic module, and the coolant manifold structure and electronic module include adjoining surfaces. One surface of the adjoining surfaces includes a plurality of coolant capillaries or passages. The coolant capillaries are sized to inhibit, for instance, via surface tension, leaking of coolant therefrom at the one surface with decoupling of the coolant manifold structure and electronic module along the adjoining surfaces.

Abstract: A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip.

Abstract: A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract: Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system. The vapor-compression refrigeration system includes an expansion component, an evaporator, a compressor, and a condenser coupled in fluid communication via a refrigerant flow path. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant extractor coupled in fluid communication with the refrigerant flow path. The extractor includes a refrigerant boiling filter and a heater. At least a portion of refrigerant passing through the refrigerant flow path passes through the refrigerant boiling filter, and the heater provides heat to the refrigerant boiling filter to boil refrigerant passing through the filter. By boiling refrigerant passing through the filter, contaminants are extracted from the refrigerant, and are deposited in the refrigerant boiling filter.

Abstract: A cooling module for cooling a semiconductor is provided and includes a land grid array (LGA) interposer, a substrate with an LGA side and a chip side, a cooler, a load frame attached to the substrate and formed to define an aperture in which the cooler is removably disposable, a spring clamp removably attachable to the load frame and configured to apply force from the load frame to the cooler such that the substrate and the cooler are urged together about the semiconductor and a load assembly device configured to urge the load frame and the LGA interposer together.

Abstract: A composite wiring circuit with electrical through connections and method of manufacturing the same. The composite wiring circuit includes a glass with first electrically-conducting through vias. The first electrically-conducting through vias pass from a top surface of the glass layer to a bottom surface of the glass layer. The composite wiring circuit further includes an interposer layer with second electrically-conducting through vias. The second electrically-conducting through vias pass from a top surface of the interposer layer to a bottom surface of the interposer layer. The second electrically-conducting through vias are electrically coupled to the first electrically-conducting through vias.

Abstract: Cooled electronic assemblies, and a method of decoupling a cooled electronic assembly, are provided. In one embodiment, the assembly includes a coolant-cooled electronic module with one or more electronic components and one or more coolant-carrying channels integrated within the module and configured to facilitate flow of coolant through the module for cooling the electronic component(s). In addition, the assembly includes a coolant manifold structure detachably coupled to the electronic module. The manifold structure, which includes a coolant inlet and outlet in fluid communication with the coolant-carrying channel(s) of the electronic module, facilitates flow of coolant through the coolant-carrying channel, and thus cooling of the electronic component(s). Coolant-absorbent material is positioned at the interface between the electronic module and the manifold structure to facilitate absorbing any excess coolant during a stepwise detaching of the manifold structure from the electronic module.

Abstract: A package structure to implement two-phase cooling includes a chip stack disposed on a substrate, and a package lid that encloses the chip stack. The chip stack includes a plurality of conjoined chips, a central inlet manifold formed through a central region of the chip stack, and a peripheral outlet manifold. The central input manifold includes inlet nozzles to feed liquid coolant into flow cavities formed between adjacent conjoined chips. The peripheral outlet manifold outputs heated liquid and vapor from the flow cavities. The package lid includes a central coolant supply inlet aligned to the central inlet manifold, and a peripheral liquid-vapor outlet to output heated liquid and vapor that exits from the peripheral outlet manifold. Guiding walls may be included in the flow cavities to guide a flow of liquid and vapor, and the guiding walls can be arranged to form radial flow channels that are feed by different inlet nozzles of the central inlet manifold.

Abstract: Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system, which includes an expansion component, an evaporator, a compressor and a condenser coupled in fluid communication. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant separator coupled in fluid communication with the refrigerant flow path. The separator includes a refrigerant cold filter and a thermoelectric array. At least a portion of refrigerant passing through the refrigerant flow path passes through the cold filter, and the thermoelectric array provides cooling to the cold filter to cool refrigerant passing through the filter. By cooling refrigerant passing through the filter, contaminants solidify from the refrigerant, and are deposited in the cold filter.

Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

Abstract: A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure.

Abstract: An assembly process for a heatsink attachment module for a chip packaging apparatus is provided and includes attaching a semiconductor chip to a substrate to form a module subassembly, placing a load frame and shim in a fixture, dispensing adhesive to the load frame and loadably placing the module subassembly chip face down in the fixture.

Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Abstract: A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.

Abstract: A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract: A cooling module for cooling a semiconductor is provided and includes a land grid array (LGA) interposer, a substrate with an LGA side and a chip side, a cooler, a load frame attached to the substrate and formed to define an aperture in which the cooler is removably disposable, a spring clamp removably attachable to the load frame and configured to apply force from the load frame to the cooler such that the substrate and the cooler are urged together about the semiconductor and a load assembly device configured to urge the load frame and the LGA interposer together.

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract: An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

Abstract: Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.