Patents by Inventor Fabrice Marinet
Fabrice Marinet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103873Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Fabrice MARINET
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Patent number: 11921834Abstract: A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.Type: GrantFiled: January 16, 2019Date of Patent: March 5, 2024Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Fabrice Marinet
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Patent number: 11853765Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: GrantFiled: April 14, 2022Date of Patent: December 26, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet
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Publication number: 20230317637Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Fabrice MARINET
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Patent number: 11715705Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.Type: GrantFiled: July 17, 2020Date of Patent: August 1, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 11663365Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.Type: GrantFiled: July 14, 2020Date of Patent: May 30, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (ALPS) SASInventors: Marc Benveniste, Fabien Journet, Fabrice Marinet
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Patent number: 11651064Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.Type: GrantFiled: March 27, 2020Date of Patent: May 16, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet
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Patent number: 11621051Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: GrantFiled: January 12, 2022Date of Patent: April 4, 2023Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SASInventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Publication number: 20220244961Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Applicants: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael PEETERS, Fabrice MARINET
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Patent number: 11387194Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.Type: GrantFiled: May 12, 2020Date of Patent: July 12, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Alexandre Sarafianos, Fabrice Marinet, Julien Delalleau
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Patent number: 11379238Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.Type: GrantFiled: March 27, 2020Date of Patent: July 5, 2022Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SASInventors: Michael Peeters, Fabrice Marinet
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Patent number: 11367720Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.Type: GrantFiled: July 22, 2019Date of Patent: June 21, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 11329011Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.Type: GrantFiled: December 7, 2020Date of Patent: May 10, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 11328098Abstract: An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.Type: GrantFiled: June 5, 2020Date of Patent: May 10, 2022Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Fabrice Marinet
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Publication number: 20220139491Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Inventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Patent number: 11322503Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.Type: GrantFiled: January 5, 2021Date of Patent: May 3, 2022Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Fabrice Marinet
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Patent number: 11250930Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.Type: GrantFiled: December 10, 2019Date of Patent: February 15, 2022Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (ROUSSET) SASInventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
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Patent number: 11003595Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.Type: GrantFiled: April 6, 2020Date of Patent: May 11, 2021Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.Inventors: Michael Peeters, Fabrice Marinet, Jean-Louis Modave
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Publication number: 20210126000Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.Type: ApplicationFiled: January 5, 2021Publication date: April 29, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Fabrice MARINET
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Publication number: 20210091015Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.Type: ApplicationFiled: December 7, 2020Publication date: March 25, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Pascal FORNARA, Fabrice MARINET