Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.

Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.

Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Abstract: A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.

Abstract: Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Abstract: Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

Abstract: Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

Abstract: Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

Abstract: In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Abstract: In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Abstract: Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.

Abstract: A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches.

Abstract: A NAND flash memory chip has a configurable interface that can communicate with a NAND flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels. Control information from the NAND flash memory controller uses a small number of channels. Double Data Rate (DDR) communication provides serial communication with adequate data transfer speed.

Abstract: Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.

Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

Abstract: A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.

Abstract: In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Abstract: A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

Abstract: Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.