Abstract: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Abstract: A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

Abstract: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.

Abstract: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

Abstract: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

Abstract: The present invention that partitions a memory array in N segments by switchably partitioning the bit lines in the array. In the exemplary embodiment, a top set of sense amps control the even bit lines and a bottom set of sense amps control the odd bit lines. The segmentation transistors turn on or off depending on the selected word line location in the array. Since bit line capacitance is mainly from the metal bit line to bit line coupling to their immediate neighbors, the bit line neighbors in the partitioned array are floating in some segments of the bit lines. The overall bit line capacitance is significantly reduced with a negligible increase in die size, resulting in reduced sensing times and enhanced read and write performance.

Abstract: In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.