Abstract: In an array substrate of the present invention, only two insulating layers are arranged on a planarization layer. Compared with conventional techniques that require at least four insulating layers arranged on the planarization layer, a number of the insulating layers arranged on the planarization layer is reduced. Therefore, a number of photomasks is reduced in a manufacturing process of the array substrate, and the manufacturing process is simplified. The present invention also provides a manufacturing method of the array substrate, and a display panel.

Abstract: The present application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving modules. A first driving signal can be output through a first output node, and at the same time, a second driving signal with a same phase as the first driving signal can be output through a second output node, and a gate driving sub-module and an in-phase output sub-module share the first output node and a pull-down node, which simplifies a circuit topology of the gate driving circuit.

Abstract: A gate driving circuit and a display panel are disclosed. A pull-up control module and a pull-down module of each stage gate driving unit are connected to a first node. A thin film transistor in the pull-up control module and/or pull-down module that is connected to the first node is an oxide thin film transistor, such that a leakage current of the first node is reduced due to the advantage of the small off-state leakage current of the oxide thin film transistor. Therefore, the voltage level of the first node can remain stable during a pull-up stage and a touch suspension stage.

Abstract: A display panel, an array substrate, and a manufacturing method thereof, wherein the array substrate includes a thin film transistor device, and an interface layer, a first transparent conductive layer, a passivation layer, and a second transparent conductive layer which are formed on the thin film transistor device in sequence. By replacing a planarization layer in the prior art with the interface layer, performing a gate re-etching process, and perforating the interface layer and the passivation layer to simultaneously form a deep via and a shallow via, a number of photomasks required to form the array substrate is reduced to 8. It effectively reduces costs of production materials and costs of photomasks.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, a metal electrode layer, a first passivation layer, a first electrode layer, a photosensitive semiconductor layer, a second passivation layer, and a second electrode layer. The first electrode layer and the photosensitive semiconductor layer are both disposed on a surface of the first passivation layer away from the metal electrode layer.

Abstract: The embodiment of the present application discloses an array substrate, a display panel, and an electronic device. The array substrate includes a substrate and includes a control element; a first electrode is connected to the control element; a PIN diode is arranged on the first electrode, The PIN diode covers at least a part of the semiconductor layer of the control element and a part of the first electrode; a second conductive layer is arranged on the PIN diode, and the second conductive layer includes a second electrode.

Abstract: A gate driving circuit and a display device are provided. The gate driving circuit includes electrically connected multi-stage driving units. The driving unit of each stage includes an input module, an output module electrically connected with the input module, a pull-down module electrically connected with the output module, and a pull-down control module electrically connected with the pull-down module. The output module is electrically connected to a stage transmission signal output terminal, and the pull-down module is electrically connected to a first control signal terminal.

Abstract: The present application provides a pixel driving circuit and a display panel. The pixel driving circuit includes an amplitude regulating module and a pulse width modulation module, where the amplitude regulating module and the pulse width modulation module are both electrically connected to a first node, so that the pulse width modulation module and the amplitude modulation module are configured to cooperate with a first data signal and a second data signal, respectively, to realize regulation of both the pulse width and the amplitude of the valid pulse of the driving current signal for driving the light emitting device to emit light. As such, the valid pulse of the driving current signal has different pulse widths and different amplitudes under correspondingly different gray scale states, so that the light emitting brightness and the light emitting duration of the light emitting device under correspondingly different gray scale states are different.

Abstract: A display panel and an electronic device are provided. The display panel includes a substrate, first touch coils, pad groups, light-emitting units, and connection lines. The first touch coils are disposed on the substrate. The pad groups are disposed on the substrate. The pad groups are disposed on a side of the first touch coils facing away the substrate. The light-emitting units are disposed on the corresponding pad groups. The connection lines are disposed insulated from the first touch coils. The connection lines are connected to two pad groups. The connection lines and the first touch coils are disposed in different layers. The connection lines intersect with the first touch coils. Intersection positions of the connection lines and the first touch coils form overlapping regions. Concave portions are defined at a surface of the connection lines close to the first touch coils.

Abstract: An array substrate, a display panel, and a display device are provided by the present application. The array substrate includes a base substrate; a light-sensitive component layer disposed on the base substrate, wherein a plurality of light-sensitive components are disposed at intervals in the light-sensitive component layer; and a first light-shielding layer disposed on the light-sensitive component layer. An orthographic projection of the first light-shielding layer on the base substrate partially overlaps with an orthographic projection of each of the light-sensitive components on the array substrate.

Abstract: An array substrate, includes: a substrate, a first metal layer, a first buffer layer, and an active layer, a gate insulating layer, a second metal layer, a first insulating layer, a third metal layer and a first planarization layer. The first metal layer is electrically connected with the first doped area of the active layer through the bridge layer of the second metal layer. The third metal layer is electrically connected with the second doped area of the active layer. The array substrate of the present disclosure reduces a size of a thin film transistor by stacking the first metal layer, the second metal layer, and the third metal layer, thereby increasing pixel density. A display panel is also provided.

Abstract: A display panel, a pixel driving circuit, and a display device are provided. Driving transistors include a first transistor and a second transistor connected in parallel. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor. A carrier mobility of the first transistor is greater than a carrier mobility of the second transistor. A driving current is affected by characteristics of the second transistor and an increase speed is slowed down, which improves a problem of color unevenness of the display panel at low brightness.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a substrate, a metal electrode layer, a first passivation layer, a first electrode layer, a photosensitive semiconductor layer, a second passivation layer, and a second electrode layer. The first electrode layer and the photosensitive semiconductor layer are both disposed on a surface of the first passivation layer away from the metal electrode layer.

Abstract: A gate driving circuit and a display device are provided. The gate driving circuit includes electrically connected multi-stage driving units. The driving unit of each stage includes an input module, an output module electrically connected with the input module, a pull-down module electrically connected with the output module, and a pull-down control module electrically connected with the pull-down module. The output module is electrically connected to a stage transmission signal output terminal, and the pull-down module is electrically connected to a first control signal terminal.

Abstract: Provided is an aqueous redox flow battery comprising a positive electrode, a negative electrode, a posolyte chamber containing a posolyte, a negolyte chamber containing a polyoxometalate as a negolyte, and a separator disposed between the posolyte chamber and the negolyte chamber, wherein the polyoxometalate has a conductivity of 65 mS cm?1 or more at ?20° C., and the aqueous redox flow battery has a power density of 250 mW cm?2 or more at ?20° C.

Abstract: A touch array substrate and a manufacturing method thereof, wherein in the touch array substrate, an active layer, an insulating layer, a pixel electrode layer, a metal layer, a planarization layer, and a common electrode layer are sequentially disposed on the buffer layer. The active layer includes a first region corresponding to a source electrode and a second region corresponding to a drain electrode. The pixel electrode layer includes a plurality of base layers. The metal layer is correspondingly disposed on the base layers. The metal layer includes a touch signal line, a data line, and a gate electrode. The common electrode layer includes a touch electrode, the source electrode, and the drain electrode.

Abstract: The present application provides a display panel and a display device. The display panel includes an array substrate, a color filter substrate, and a colloid layer. The array substrate includes a thin film transistor layer and a passivation layer. The passivation layer includes at least one first connection element. The color filter substrate is disposed opposite to the array substrate. The colloid layer is arranged between the passivation layer and the color filter substrate, the colloid layer is connected to the first connection element, and the colloid layer and the first connection element couple the array substrate to the color filter substrate.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and a switch component and a light-sensing component adjacent to each other and disposed on the substrate. The switch component includes a first semiconductor disposed on the substrate. The light-sensing component includes a second semiconductor disposed on a same layer as the first semiconductor and a light-sensing electrode disposed on a side of the second semiconductor away from the substrate and connected to the second semiconductor. The light-sensing electrode and the second semiconductor constitute a Schottky knot.

Abstract: An array substrate, a manufacturing process of an array substrate, and a display panel are disclosed. The array substrate includes a substrate and a photosensitive element. The photosensitive element is disposed on the substrate and includes a doped semiconductor layer, an intrinsic semiconductor layer, and a transparent electrode layer sequentially stacked. By improving an internal structure of the photosensitive element, light absorption by an incident interface of the intrinsic semiconductor layer can be increased, so that sensitivity of the photosensitive element is enhanced.

Abstract: A light-sensitive sensor, an array substrate, and an electronic equipment are provided. The light-sensitive sensor includes a third metal layer, a second semiconductor layer, and a fourth metal layer. The third metal layer includes a second gate. The second semiconductor layer includes conductive portions, and the conductive portions are disposed at both ends of the second semiconductor layer. The fourth metal layer disposed on the second semiconductor layer, and the fourth metal layer includes a second source and a second drain.