Abstract: A display panel and a manufacturing method thereof, and a display device are provided. The display panel includes a backlight module and an array substrate. The array substrate includes an insulation structure is located in the opening region. A first groove is defined at a side of the insulation structure away from the backlight module. A first insulation layer and a second insulation layer are filled in the first groove. The second insulation layer is located on a side of the first insulation layer close to the backlight module, and a refractive index of the second insulation layer is less than a refractive index of the first insulation layer.

Abstract: A foldable display device and a flexible display assembly are provided. The foldable display device includes a casing frame, a flexible display module arranged on the casing frame, and a pull-back device; the casing frame includes a first frame body and a second frame body hinged with the first frame body, and a hinged portion between the first and second frame bodies corresponds to a bending area of the flexible display module; a support plate is arranged on one side of the flexible display module facing away from a display side, the support plate is arranged close to a first end of the flexible display module and is slidably connected to the second frame body, and a portion of the flexible display module close to a second end is fixed on the first frame body; the pull-back device is arranged between the support plate and the second frame body.

Abstract: The present disclosure provides a quantum dot particle aggregate and a preparation method therefor, a preparation method for a light conversion device, and quantum dot particles. The preparation method for the quantum dot particle aggregate includes: mixing a plurality of first polymer particles, a first quantum dot solution and a second polymer solution, and drying to obtain an aggregate containing a plurality of quantum dot particles A, where each of the quantum dot particles A includes a core of a first polymer particle and a shell of a second polymer formed by the second polymer, a plurality of first quantum dots are positioned in the shell of the second polymer, and the first polymer particle has a minimum dimension greater than or equal to 0.3 mm. The process reduces the damage to quantum dots and can prolong the life time of application products of quantum dots.

Abstract: A negative electrode material on which a metal element is gradient-doped and an application thereof. The negative electrode material comprises a granular silica/M composite material on which a metal element M is gradient-doped. The general formula of the silica is SiOx, wherein 0<x<2. The metal element M comprises one or more among Na, Mg, Al, Li, Mn, Fe, Co, Ni, Cu, or Zn. In the negative electrode material, the content of the metal element M gradually decreases from the surface to the core, presenting a doping distribution having a continuous concentration gradient. The general chemical formula of the silica/M composite material is SiMyOz, wherein 0<y<10 and 0<z<10.

Abstract: A silicon-based negative electrode material containing a silicate skeleton, a negative electrode plate and a lithium battery. The silicon-based negative electrode material comprises a modified silicon monoxide material having a dispersedly distributed silicate material inside same. The general formula of the modified silicon monoxide material is MxSiOy, with 1<x<6, 3<y<6, element M comprising one or more of Mg, Ni, Cu, Zn, Al, Na, Ca, K, Li, Fe and Co, and the grain size being 0.5-100 nm. In the modified silicon monoxide material, the content of the silicate material is 5-60% of the total mass of the modified silicon monoxide material. The dispersedly distributed silicate material forms a skeleton structure of the silicon-based negative electrode material, does not undergo a physicochemical reaction along with the lithium removal and lithium intercalation of the silicon-based negative electrode material in the cycle process, and maintains the original structure thereof after multiple cycles.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: A retimer application system is provided, which includes a primary chip, a retimer, and a secondary chip. After first link training is completed, the retimer is configured to store, in a first storage area, an equalization parameter corresponding to each rate during the first link training, and data stored in the first storage area is not lost when the retimer performs a reset operation. The retimer is further configured to: receive a reset indication, and perform the reset operation according to the reset indication. The primary chip and the secondary chip are configured to perform second link training triggered by the reset indication. During the second link training, the retimer is further configured to: invoke the equalization parameter, and transparently transmit a training sequence in the second link training to the primary chip or the secondary chip based on the equalization parameter.

Abstract: A hospital human resource information management file cabinet is provided, including a support base plate, a lower surface of which is fixedly connected to upper surfaces of three fan assemblies; left ends of the three fan assemblies are respectively connected to outer surfaces of three first conduits, and front ends of the three first conduits are in communication with back ends of three second conduits. The file cabinet speeds up air flow rate on surfaces of the files therein, prevents moisture causing damage to the files, reduces information loss, and continuously treats the moisture inside, which in turn guarantees the service life of the file cabinet.

Abstract: A storage device includes a hard disk backplane, a first cascading board, and a hard disk array. The hard disk array includes a plurality of hard disks, and is located on a first side of the hard disk backplane. The first cascading board is a field-replaceable unit FRU, and is located on a second side of the hard disk backplane.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase.

Abstract: Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, executing, by the master processing core, a task update instruction to obtain a to-be-executed task segment; receiving, by a processing core for executing the task, the to-be-executed task segment, wherein the processing core for executing the task includes the master processing core and/or the slave processing core; executing, by the processing core for executing the task, the to-be-executed task segment; and in response to completion of execution of the to-be-executed task segment, sending, by the processing core for executing the task, a synchronization request signal, wherein the synchronization request signal is configured to trigger generation of the synchronization signal.

Abstract: Disclosed is a data processing apparatus, chip, and data processing method. The data processing apparatus includes: a plurality of processing cores having a preset execution sequence, the plurality of processing cores including a head processing core and at least one other processing core; wherein the head processing core is configured to send an instruction, and receive and execute a program obtained according to the instruction; and each of the other processing cores is configured to receive and execute a program sent by a previous processing core in the preset execution sequence.

Abstract: Disclosed is a task allocation method, apparatus, electronic device, and computer-readable storage medium. The task allocation method includes: in response to receiving a synchronization signal, determining, by the microprocessor, whether allocation of a task segment to the processing core is required according to the synchronization signal, wherein the task segment is a part of a task; in response to the allocation of the task segment to the processing core being required, instructing, by the microprocessor, to allocate the task segment to the processing core; receiving, by the processing core, the task segment; and in response to satisfying a first preset condition, sending, by the processing core, a synchronization request signal, wherein the synchronization request signal is configured to trigger the generation of the synchronization signal.

Abstract: The invention discloses an NDT device for pipeline, belonging to the field of NDT, including a mobile carrier, which moves with fluid in pipeline or is moved by an actuator; a probe testing assembly, which includes a testing component installed on the mobile carrier and having a testing element in which testing probe is encapsulated; a data processing unit, a first signal conditioning unit and a second signal conditioning unit, wherein the testing probe includes an excitation coil, a receiving coil and a passive resonance coil between the excitation coil and the receiving coil. For the invention, no more magnetizing treatment device is needed for testing, so that the system volume is greatly reduced, thereby reducing the requirement of the testing system of the invention on the internal cleanliness of a pipeline, improving flexibility of equipment in the pipeline of the testing system, and greatly reducing the system cost.

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

Abstract: Embodiments of wireless audio systems and methods for operation mode switch of wireless headphones are disclosed herein. In one example, a wireless audio system includes a first wireless headphone and a second wireless headphone. The first wireless headphone is configured to establish a first short-range wireless link with an audio source; transmit, to a second wireless headphone, link information associated with the first short-range wireless link; and remove the first short-range wireless link with the audio source in response to the second wireless headphone successfully establishing a second short-range wireless link with the audio source based on the link information. The second wireless headphone is configured to receive, from the first wireless headphone, the link information associated with the first short-range wireless link; and establish the second short-range wireless link with the audio source based on the link information.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: Embodiments of the present disclosure provide a data processing method, apparatus, electronic device and computer-readable storage medium. The data processing method includes: receiving, by a processing core, a synchronization signal; determining, by the processing core, according to the synchronization signal, a first storage area used by a self-task of the processing core and a second storage area used by a non-self-task of the processing core; wherein the first storage area differs from the second storage area; accessing the first storage area to execute the self-task and accessing the second storage area to execute the non-self-task by the processing core. Through the above method, the storage areas corresponding to different tasks of the processing core are separated, which solves the technical problems of complex data consistency processing mechanism and low processing efficiency caused by reading from and writing into the same storage area in the existing technology.

Abstract: A method realizes synchronous playing of audio data from an audio source by two or more wireless speakers. The method includes receiving at each of the wireless speakers first audio data packets sent by the audio source and determining a respective first time point for the receiving of the first audio data packets; processing the first audio data packets at each of the wireless speakers to generate respective second audio data packets, the second audio data packets each including audio data to be played with a fixed data length; setting a delayed play time and obtaining a playing time point at each of the wireless speakers, the obtaining of the playing time point being based on the respective first time point and the respective delayed play time; and playing the second audio data packets at each of the wireless speakers at the respective playing time point.