Abstract: Embodiments of the present disclosure provide a display panel, a display device including the display panel and a method for fabricating the display panel. The display panel comprises a display area and a non-display area surrounding the display area. The display panel includes a pixel array, an edge of which defines a boundary between the display area and the non-display area, wherein the non-display area includes a first area and a second area arranged in sequence in a direction away from the pixel array; a compensation circuit configured to compensate for a parasitic capacitance of pixel in the pixel array, and including a first portion located in the first area and a second portion located in the second area; and a first shift register located in the second area. The second portion of the compensation circuit is aligned with the first shift register circuit in a circumferential direction of the pixel array.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device.

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.

Abstract: Disclosed is a system and method for communication using an efficient fiber-to-chip grating coupler with a high coupling efficiency.

Abstract: A method and system for generating a physical layout for a grating coupler integrated in a photonically-enabled circuit are disclosed herein. In some embodiments, the method receives a parametrized wavelength, a parametrized first refractive index, a parametrized second refractive index, a parametrized taper length, a parametrized width, a parametrized grating length, and a parametrized incident angle of the optical beam incident onto the grating coupler and generates a physical layout for the grating coupler based on the received parametrized inputs, the generating of the physical layout is according to a predefined model, and outputs the physical layout of the grating coupler for manufacturing under a semiconductor fabrication process.

Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes a base substrate including a display region and a peripheral region located on at least one side of the display region, and a first gate drive circuit, the first gate drive circuit includes a first clock signal line, a second clock signal line and N shift register units that are cascaded; each shift register unit of the N shift register units includes a first output circuit; the first output circuit includes the first output transistor, the orthographic projection of the second clock signal line on the base substrate is located between an orthographic projection of the first output transistor on the base substrate and the orthographic projection of the first clock signal line on the base substrate. The display substrate can reduce load of the first clock signal line and the second clock signal line.

Abstract: A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.

Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.

Abstract: A memory device is provided, including an array of bit cells and a set of tracking cells. The set of tracking cells is arranged adjacent to the array of bit cells along a first direction. The set of tracking cells includes a set of first tracking cells configured to perform a read tracking operation and a set of second tracking cells configured to perform a write tracking operation and arranged adjacent to the set of first tracking cells along a second direction. First tracking cells in the set of first tracking cells are coupled in series with each other and arranged along the second direction, and second tracking cells in the set of second tracking cells are coupled in series with each other and arranged along the second direction.

Abstract: The present invention provides a retractable camera module, including a housing, a lens assembly, a support assembly, a driving assembly, and an exterior part covered on the housing. A bulge portion is arranged on an outer wall of a top plate in the housing; a first groove matched with the bulge portion is formed in an inner wall of the exterior part; the support assembly includes a lifting plate connected to the lens assembly, a guide rod penetrating through the lifting plate and fixedly connected between the bulge portion and a bottom plate, and at least two elastic members elastically connected between the lifting plate and the bottom plate. the present invention provides a retractable camera module which occupies a small space and can ensure the extending and retracting steadiness and achieves better optical characteristics.

Abstract: A lithium battery power display method and corresponding system, the method includes: during charging process of lithium battery, periodically calculating SOC value charged in this charging through a current integration method (S10); obtaining a sum of the SOC value displayed before charging and the SOC value charged, determining whether it is in a predetermined charging platform area (S11); when determination result is in the predetermined charging platform area and it is determined the correction trigger condition is met, a correction coefficient is calculated according to pre-calibrated formula, the SOC value to be displayed is obtained by correcting the SOC value charged with the correction coefficient, the correction coefficient is positive number less than 1 (S12); displaying the SOC value to be displayed (S13). Solve virtual electricity caused by large SOC error in non-full charge and discharge state of lithium batteries, improve experience of lithium battery electric vehicles.

Abstract: A package structure comprises photonic dies and an interposer structure. Each photonic die includes a dielectric layer and a first grating coupler embedded in the dielectric layer. The interposer structure is disposed below the photonic dies. The interposer structure includes an oxide layer and a second grating coupler embedded in the oxide layer. The photonic dies are optically coupled through the first grating couplers of the photonic dies and the second grating coupler of the interposer structure.

Abstract: Disclosed is a display substrate, including: a base including a display region and a peripheral region; sub-pixels in the display region; data lines in at least the display region and extending in a first direction and electrically connected to the sub-pixels; gate lines in at least the display region and extending in a second direction intersecting with the first direction, and electrically connected to the sub-pixels; pads in the peripheral region; data leads in the peripheral region and electrically connected to the data lines and the pads; a gate driver circuit in the peripheral region and electrically connected to the gate lines; gate drive lines in the peripheral region and electrically connected to the gate driver circuit; gate leads in the peripheral region and extending in the first direction, which are electrically connected to the gate drive lines and the pads and located between the data leads.

Abstract: In an embodiment, a phase shifter includes: a light input end; a light output end; a p-type semiconductor material, and an n-type semiconductor material contacting the p-type semiconductor material along a boundary area, wherein the boundary area is greater than a length from the light input end to the light output end multiplied by a core width of the phase shifter.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: Provided is a display substrate. In the display substrate, at least one data-select circuit group may control a data line lead to transmit a data signal to at least two data lines by time division in response to switch control signals supplied by at least two switch control lines at different time periods. A plurality of connecting portions that are electrically connected to a first power bus and a plurality of power lines may extend along the region between a plurality of the data-select circuit groups.

Abstract: Provided is a display panel, including: a base substrate, including a display area and a peripheral area surrounding the display area; a plurality of pixel units, disposed in the display area; a barrier structure, disposed in the peripheral area; at least one first power line, disposed in the peripheral area; and, a row drive circuit, disposed in the peripheral area, wherein orthographic projections of any two of the following structures on the base substrate are at least partially overlapped with each other: the barrier structure, the at least one first power line, and the row drive circuit.