Patents by Inventor Fernando Gonzalez

Fernando Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9089742
    Abstract: An automatic collection method for collecting one or more spherical game elements that may be struck by a striking element is disclosed.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 28, 2015
    Assignee: Foxtenn Bgreen, S.L.
    Inventors: Javier Simón Vilar, Fernando González Minguez
  • Publication number: 20150141037
    Abstract: Systems and methods disclosed herein may include tracking one or more geo-fences using a GNSS hardware processor within a computing device. The tracking may use at least one GNSS signal. State changes of the one or more geo-fences during the tracking may be saved in a shared state database. The shared state database may be shared between the GNSS hardware processor and an application processor within the computing device. Upon detecting a deterioration of the at least one GNSS signal, tracking the one or more geo-fences may be switched from using the GNSS hardware processor to using the application processor. After the switching, an initial state of each of the one or more geo-fences may be set by using states currently stored in the shared state database prior to the switching.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Microsoft Corporation
    Inventors: Sanjib Saha, Fernando Gonzalez, Shaun Hedrick, Parmjeet Singh, Ashish Gadre, Frank Gorgenyi, Mark Inderhees, Janet Schneider, Stuart Harper
  • Publication number: 20150064271
    Abstract: New Lactococcus lactis strains, NRRL B-50571 and NRRL B-50572, and a bacterial preparation containing the same, have the ability to produce bioactive peptides that reduce blood pressure, lower LDL-cholesterol (bad cholesterol) and present antioxidant properties for better cardiovascular health. These biologically active peptides may be produced within the food for the production of a food product, such as a functional food, or they may be produced from protein sources and subsequently added to a food as part of the formulation or as part of a food supplement or a pharmaceutical preparation.
    Type: Application
    Filed: October 8, 2014
    Publication date: March 5, 2015
    Inventors: Belinda Vallejo Galland, Aarón Fernando González Córdova, Jóse Carlos Rodríguez Figueroa
  • Publication number: 20150050255
    Abstract: New Lactococcus lactis strains, NRRL B-50571 and NRRL B-50572, and a bacterial preparation containing the same, have the ability to produce bioactive peptides that reduce blood pressure, lower LDL-cholesterol (bad cholesterol) and present antioxidant properties for better cardiovascular health. These biologically active peptides may be produced within the food for the production of a food product, such as a functional food, or they may be produced from protein sources and subsequently added to a food as part of the formulation or as part of a food supplement or a pharmaceutical preparation.
    Type: Application
    Filed: October 28, 2014
    Publication date: February 19, 2015
    Inventors: BELINDA VALLEJO GALLAND, AARÓN FERNANDO GONZÁLEZ CÓRDOVA, JÓSE CARLOS RODRÍGUEZ FIGUEROA
  • Publication number: 20150051159
    Abstract: New Lactococcus lactis strains, NRRL B-50571 and NRRL B-50572, and a bacterial preparation containing the same, have the ability to produce bioactive peptides that reduce blood pressure, lower LDL-cholesterol (bad cholesterol) and present antioxidant properties for better cardiovascular health. These biologically active peptides may be produced within the food for the production of a food product, such as a functional food, or they may be produced from protein sources and subsequently added to a food as part of the formulation or as part of a food supplement or a pharmaceutical preparation.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 19, 2015
    Inventors: Belinda Vallejo Galland, Aarón Fernando González Córdova, Jóse Carlos Rodríguez Figueroa
  • Publication number: 20140370909
    Abstract: Various different areas of interest are identified, these areas being geographic areas that are also referred to as geo-fences. Whether a computing device is in a geo-fence can be determined based on the location of the geo-fence and the location of the computing device. The location of a computing device can be determined using various different location determination techniques, such as wireless networking triangulation, cellular positioning, Global Navigation Satellite System positioning, network address positioning, and so forth. Various power saving techniques are implemented to determine which techniques are used and when such techniques are used to reduce power consumption in the computing device.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Lanny D. Natucci, JR., Janet L. Schneider, Mark A. Inderhees, Robert R. Dufalo, Jonathan M. Kay, Cristina del Amo Casado, Sanjib Saha, Fernando Gonzalez, Priyanka B. Vegesna
  • Publication number: 20140370911
    Abstract: A device location is determined, and the location of an area of interest that is a geographic area referred to as a geo-fence is identified. Multiple geo-fences can be identified by the device, and different geo-fences can be associated with different programs on the device. An operating system of the device implements multiple different periods of operation for the device, including a conservation period during which certain programs are not typically scheduled to run, and an execution period during which such programs are typically scheduled to run. A system identifies geo-fence events, which occur when the device enters or exits the geo-fence. The system maintains a record of the geo-fence events for each of multiple geo-fences, and provides to a program selected ones of those geo-fence events at a time when the program is scheduled to run on the device during an execution period of the operating system.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Frank Gorgenyi, Daniel Estrada Alva, Fernando Gonzalez, Sanjib Saha
  • Publication number: 20140370910
    Abstract: The location of a computing device is determined, and the location of an area of interest that is a geographic area referred to as a geo-fence is identified. The accuracy of the determined location of the computing device has an associated uncertainty, so the exact position of the computing device cannot typically be pinpointed. In light of this, the uncertainty associated with the determined location is evaluated relative to the size of the geo-fence in order to determine whether the computing device is inside the geo-fence or outside the geo-fence. Based on this determination, various actions can be taken if the user is entering the geo-fence, exiting the geo-fence, remaining in the geo-fence for at least a threshold amount of time, and so forth.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Inventors: Lanny D. Natucci, JR., Janet L. Schneider, Mark A. Inderhees, Frank Gorgenyi, Stuart J. Harper, Cristina del Amo Casado, Fernando Gonzalez, Sanjib Saha, Shaun C. Hedrick
  • Patent number: 8872219
    Abstract: A multi-dimensional solid state lighting (SSL) device array system and method are disclosed. An SSL device includes a support, a pillar having several sloped facets mounted to the support, and a flexible substrate pressed against the pillar. The substrate can carry a plurality of solid state emitters (SSEs) facing in various directions corresponding to the sloped facets of the pillar. The flexible substrate can be a flat substrate prepared using planar mounting techniques, such as wirebonding techniques, before bending the substrate against the pillar.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Alan Mondada, Fernando Gonzalez, Willard L. Hofer
  • Patent number: 8865155
    Abstract: New Lactococcus lactis strains, NRRL B-50571 and NRRL B-50572, and a bacterial preparation containing the same, have the ability to produce bioactive peptides that reduce blood pressure, lower LDL-cholesterol (bad cholesterol) and present antioxidant properties for better cardiovascular health. These biologically active peptides may be produced within the food for the production of a food product, such as a functional food, or they may be produced from protein sources and subsequently added to a food as part of the formulation or as part of a food supplement or a pharmaceutical preparation.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: October 21, 2014
    Assignees: Centro de Investigacion en Alimentacion y Desarrollo, A.C. (CIAD)
    Inventors: Belinda Vallejo Galland, Aarón Fernando González Córdova, José Carlos Rodríguez Figueroa
  • Publication number: 20140219017
    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra V. Mouli
  • Publication number: 20140154217
    Abstract: New Lactococcus lactis strains, NRRL B-50571 and NRRL B-50572, and a bacterial preparation containing the same, have the ability to produce bioactive peptides that reduce blood pressure, lower LDL-cholesterol (bad cholesterol) and present antioxidant properties for better cardiovascular health. These biologically active peptides may be produced within the food for the production of a food product, such as a functional food, or they may be produced from protein sources and subsequently added to a food as part of the formulation or as part of a food supplement or a pharmaceutical preparation.
    Type: Application
    Filed: September 27, 2012
    Publication date: June 5, 2014
    Applicants: CENTRO DE INVESTIGACION EN ALIMENTACION Y DESARROLLO, A.C. (CIAD)
    Inventors: BELINDA VALLEJO GALLAND, AARÓN FERNANDO GONZÁLEZ CÓRDOVA, JOSÉ CARLOS RODRÍGUEZ FIGUEROA
  • Patent number: 8724372
    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra V. Mouli
  • Publication number: 20140072810
    Abstract: The process is characterised in that it comprises at least one sol-gel layer with a maximum thickness of 800 nm, where said sol-gel layer comprises nanoparticles with a laminar crystal structure, and where each sol-gel layer is obtained from a silicon alkoxide solution; preparation of a dispersion that comprises at least one type of particles with a spherical, fibrillar or laminar morphology, and a laminar crystal structure, wherein at least one of the dimensions, thickness or diameter, of said particles is less than 400 nm; addition of the dispersion prepared to the solution; deposition of the suspension on said substrate; thermal treatment of the substrate; and, in the case of multilayer coatings, optionally, the addition of high-dimensional particles and repetition of the steps, provided that the thermal treatment of the last layer, or outer layer, is performed at a temperature equal to or greater than that of the preceding layer. The invention also relates to the sol-gel coating thus obtained.
    Type: Application
    Filed: February 21, 2012
    Publication date: March 13, 2014
    Applicant: Roca Sanitario, S.A.
    Inventors: Fernando Gonzalez-Juarez, Antonio Jorge De Alburquerque Sanchez, Jordi Balcells Villanueva, Alberto Quintana Bartual, Jose Francisco Fernandez Lozano, Esther Enriquez Perez, Miguel Angel De La Rubia Lopez, Miguel Angel Garcia Garcia-Tunon, Miguel Angel Rodriguez Barbero
  • Publication number: 20140036584
    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
    Type: Application
    Filed: October 10, 2013
    Publication date: February 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra V. Mouli
  • Patent number: 8643110
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Publication number: 20140021550
    Abstract: This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.
    Type: Application
    Filed: September 20, 2013
    Publication date: January 23, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Patent number: 8582350
    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: November 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Chandra V. Mouli
  • Publication number: 20130292712
    Abstract: A multi-dimensional solid state lighting (SSL) device array system and method are disclosed. An SSL device includes a support, a pillar having several sloped facets mounted to the support, and a flexible substrate pressed against the pillar. The substrate can carry a plurality of solid state emitters (SSEs) facing in various directions corresponding to the sloped facets of the pillar. The flexible substrate can be a flat substrate prepared using planar mounting techniques, such as wirebonding techniques, before bending the substrate against the pillar.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Alan Mondada, Fernando Gonzalez, Willard L. Hofer
  • Patent number: 8551823
    Abstract: This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: October 8, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez