Abstract: A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determined for each proximity corrected physical design. Shapes with a unique design (e.g., in boundary cells and unique instances of books) are tagged and the design is unnested. Only the unique shapes are proximity corrected in the unnested design, which may be used to make a mask for fabricating IC chips/wafers.

Abstract: A novel method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules.

Abstract: A method and computer system is described for designing a conflict-free altPSM layout by first constructing a planar interlock graph without predefining phase shift shapes. Feature nodes of the graph represent critical elements, while connection nodes of the graph represent phase shape interactions. A pattern analysis of the interlock graph is performed to identify layout violations. Solutions for resolving layout conflicts are applied to the layout resulting in at least one conflict-free altPSM layout. Phase shapes are then applied to the conflict-free altPSM layout. Selection of an optimal solution can be made based on cost analysis.

Abstract: The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

Abstract: A method and computer system is described for designing a conflict-free altPSM layout by first constructing a planar interlock graph without predefining phase shift shapes. Feature nodes of the graph represent critical elements, while connection nodes of the graph represent phase shape interactions. A pattern analysis of the interlock graph is performed to identify layout violations. Solutions for resolving layout conflicts are applied to the layout resulting in at least one conflict-free altPSM layout. Phase shapes are then applied to the conflict-free altPSM layout. Selection of an optimal solution can be made based on cost analysis.

Abstract: In connection with the manufacture of chips having partitioned logic, a partitioned mask layout approach. This approach provides the chip exposure pattern as a set of partitions corresponding to macros or core functions and also handles glue logic and interconnect. A result of this approach is a simplified, cost-effective process that does not defer customization to other, potentially more time-consuming and inefficient tasks.

Abstract: A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.

Abstract: A method for converting an integrated circuit design to a phase-shift complaint mask design. The method comprises the steps of locating features of the integrated circuit that violate predetermined design criteria converting error flags to physical marker shapes, modifying the located features using layout modification system technology based on a predetermined cost constraint, determining if all violations are corrected, and either changing the cost constraint to a higher cost constraint if violations still exist and repeating the process or terminating the conversion if all violations are corrected.

Abstract: An existing layout is modified to ensure compliance with design rules and any user-defined rules by deriving a horizontal constraint model and a vertical constraint model. For each of the vertical and horizontal orientations in turn, violations of the rules are identified. For each orientation in turn, the violations are removed in such a way that objects in the layout are moved the least amount necessary. A given object may also be inserted into an existing layout in such a way that perturbation of objects in the existing layout is minimized by exploring solutions allowing for object merger and non-merger solutions and choosing the best one based on predetermined criteria. Given a group of objects, a layout may also be created in such a way that successive objects are placed to minimize movement of objects already placed.