Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may include a plurality of mutually adhered regions. The stiffeners may be configured to prevent torsional flexion or bending of the connective structure to which they are to be secured, to reinforce sprocket or indexing holes in connective structures or to include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude.

Abstract: A method of electrically connecting corresponding contact pads of semiconductor device components to each other includes interconnecting first and second members of an interconnection element. The first and second members respectively protrude from first and second semiconductor device components, with a conductive element of each member in communication with a contact pad of its corresponding semiconductor device component. Each member of the interconnection element also includes an insulative coating, or shell. When the first and second member of an interconnection element are interconnected, the insulative coating, or shell, may substantially cover or encase the conductive elements of the interconnection element.

Abstract: A method for fabricating an electrical interconnection element, or conductive structure, includes disposing a jacket of a first member of the electrical interconnection element laterally around a contact of a semiconductor device structure and introducing conductive material into the jacket. The jacket, which may be electrically insulative, may include a plurality of adjacent, mutually adhered regions. Such regions may be formed by programmed material consolidation processes, such as stereolithography, in which material is selectively consolidated in a manner controlled by a program. The first member is configured to interconnect with a second member of the electrical interconnection element, which may be secured to and electrically communicate with a contact of another semiconductor device component.

Abstract: A carrier (e.g., a carrier substrate, such as a circuit board, etc.) may be modified to include a solder mask on a surface thereof. The solder mask, which may extend to or beyond an edge of the carrier, includes an opening that exposes at least one contact area of the carrier. The opening of the solder mask is configured and positioned such that a conductive element (e.g., a bond wire), at least a portion of which extends laterally, that may protrude from the contact area will be at least partially laterally surrounded by the solder mask. A retention element may be secured to the solder mask, over the conductive element and a portion of the opening of the solder mask, with a portion of the opening remaining exposed beyond the retention element to facilitate the introduction of encapsulant material into the opening and around the conductive element. Assemblies that include these features and assembly methods are also disclosed.

Abstract: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may include a plurality of mutually adhered regions. The stiffeners may be configured to prevent torsional flexion or bending of the connective structure to which they are to be secured, to reinforce sprocket or indexing holes in connective structures or to include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude.

Abstract: A semiconductor device assembly having a lead frame and a semiconductor die configured to be attached to each other is disclosed. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A marking for a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The marking is configured to contrast visually with a semiconductor device component, and may include features that are configured to protrude from the semiconductor device component recessed features to provide desired indicia. Materials that contrast visually with one another may also be used to form the marking.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second portion extending from a second side thereof to minimize the shear stress between the material extruded therethrough and the stencil. The stencil allows for material to be extruded through the top of the stencil to the surface of the substrate and not contact the wall of the second portion of the aperture of the stencil. Since the material only contacts a small area of the first portion of the aperture near the top of the stencil, the material remains on the substrate and not in the aperture of the stencil.

Abstract: A method for fabricating an electronic component, such as a semiconductor device, carrier, or other semiconductor device component, includes providing a support around at least a portion of a contact of the electronic component. The support is configured to receive at least a portion of a conductive structure that is to be secured to the contact. The support may also be configured to define a shape of at least a portion of the conductive structure. The support may be preformed, then placed on the electronic component, or formed on the electronic component. A programmed material consolidation process may be used to form the support.

Abstract: Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of the present invention, a mold compound is interspersed between conductive bumps on the active face of a wafer to provide support and protection for the wafer structure both during and after a process of removing the wafer's inactive back side silicon surface. The mold compound also serves to preserve the integrity of the conductively bumped aspects of the wafer during subsequent processing and may, after the wafer is diced, act as all or part of an underfill material for flip-chip applications.

Abstract: A solder mask includes an opening through which intermediate conductive elements may be positioned between bond pads of a semiconductor die exposed through an aligned opening in a carrier substrate to which the solder mask is secured and corresponding contact areas of the carrier substrate. An assembly is formed by forming the solder mask on or securing the solder mask to the carrier substrate. The semiconductor die is attached to the carrier substrate such that bond pads of the semiconductor die are exposed through the aligned openings in the carrier substrate and solder mask. Intermediate conductive elements are used to electrically connect the bond pads to corresponding contact areas on the carrier substrate. An encapsulant material is introduced into an area defined by the solder mask and carrier substrate openings such that the intermediate conductive elements and semiconductor die surface within the aligned openings are encapsulated.

Abstract: A polymer masking flux for fabricating external contacts on semiconductor components includes a polymer resin, a fluxing agent and a curing agent. The flux is configured to clean contact pads for the external contacts, and to hold the external contacts on the contact pads during a reflow bonding process. The flux is also configured to cure or polymerize, to form donut shaped polymer support members for the external contacts. In addition, the flux is configured to mask conductive traces in electrical communication with the contact pads, and to electrically insulate the external contacts from the conductive traces. The external contacts can be pre-formed solder balls, or deposited solder bumps. In the case of solder bumps, the flux can include solder particles configured to coalesce into the solder bumps.

Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.

Abstract: A polymer masking flux for fabricating external contacts on semiconductor components includes a polymer resin, a fluxing agent and a curing agent. The flux is configured to clean contact pads for the external contacts, and to hold the external contacts on the contact pads during a reflow bonding process. The flux is also configured to cure or polymerize, to form donut shaped polymer support members for the external contacts. In addition, the flux is configured to mask conductive traces in electrical communication with the contact pads, and to electrically insulate the external contacts from the conductive traces. The external contacts can be pre-formed solder balls, or deposited solder bumps. In the case of solder bumps, the flux can include solder particles configured to coalesce into the solder bumps.

Abstract: A polymer masking flux for fabricating external contacts on semiconductor components includes a polymer resin, a fluxing agent and a curing agent. The flux is configured to clean contact pads for the external contacts, and to hold the external contacts on the contact pads during a reflow bonding process. The flux is also configured to cure or polymerize, to form donut shaped polymer support members for the external contacts. In addition, the flux is configured to mask conductive traces in electrical communication with the contact pads, and to electrically insulate the external contacts from the conductive traces. The external contacts can be pre-formed solder balls, or deposited solder bumps. In the case of solder bumps, the flux can include solder particles configured to coalesce into the solder bumps.

Abstract: A method and system for fabricating solder bumps on semiconductor components are provided. The component can be a wafer, a die, a package, or a BGA substrate. The component is provided with electrodes, such as aluminum bond pads, on which the solder bumps are formed. Initially, the electrodes are cleaned and activated for a subsequent electroless deposition processes. Next, adhesion metal layers are electrolessly deposited on the electrodes to provide adhesion. and a barrier layer on the electrodes. Next, solder wettable layers are electrolessly deposited on the adhesion metal layers, to provide wettable surfaces for depositing the solder bumps. Preferred materials include nickel for the adhesion metal layers, and palladium for the solder wettable layers. A wave soldering process is then used to deposit solder bumps on the solder wettable layers.

Abstract: A method and system for fabricating solder bumps on semiconductor components are provided. The component can be a wafer, a die, a package, or a BGA substrate. The component is provided with electrodes, such as aluminum bond pads, on which the solder bumps are formed. Initially, the electrodes are cleaned and activated for a subsequent electroless deposition processes. Next, adhesion metal layers are electrolessly deposited on the electrodes to provide adhesion and a barrier layer on the electrodes. Next, solder wettable layers are electrolessly deposited on the adhesion metal layers, to provide wettable surfaces for depositing the solder bumps. Preferred materials include nickel for the adhesion metal layers, and palladium for the solder wettable layers. A wave soldering process is then used to deposit solder bumps on the solder wettable layers.

Abstract: A semiconductor package and method for fabricating the package are provided. The package includes a housing having individual channels, each adapted to retain a semiconductor die in electrical communication with electrical connectors. The dice can include solder bumps, formed on electrodes, using electroless deposition and wave soldering. For fabricating the package, the dice can be inserted into the channels, with the electrical connectors on the housing proximate to the solder bumps on the dice. The solder bumps can then be reflowed to form bonded connections with the electrical connectors. In an alternate embodiment, conductive adhesive bumps, rather than solder bumps, are formed on the dice to provide compliant connections with the electrical connectors on the housing. In addition, the conductive adhesive bumps can be cured while in contact with the electrical connectors to form bonded connections.