Abstract: Circuits, methods, and apparatus for graphically displaying performance metrics of processors such as graphics processing units in multiple processor systems. Embodiments of the present invention may provide metric information regarding operations in alternate-frame rendering, split-frame rendering, or other modes of operation. One embodiment of the present invention provides data in split-frame rendering mode including load balancing, graphics processing unit utilization, frame rate, and other types of system information in a graphical manner. Another exemplary embodiment of the present invention provides graphical information regarding graphics processing unit utilization, frame rate, and other system information while operating in the alternate-frame rendering mode.

Abstract: A graphics processing unit implements conditional rendering by putting itself in a state in which it does not execute any rendering commands. Once the graphics processing unit is placed in this state, all subsequent rendering commands are ignored until another rendering command explicitly removes the graphics processing unit from this state. Conditional rendering commands enable the graphics processing unit to place itself in and out of this state based upon the value of a flag in memory. Conditional rendering commands can include conditions that must be satisfied by the flag value in order to change the state of the graphics processing unit. The value of the flag can be set by the graphics processing unit itself, a second graphics processing unit, a graphics coprocessor, or the central processing unit. This enables a wide variety of conditional rendering methods to be implemented.

Abstract: On-demand memory synchronization is provided for peripheral subsystems, including graphics systems, that include multiple co-processors operating in parallel. A region of master memory (memory associated with one of the peripheral co-processors) is copied, on demand, to a corresponding region of a different memory associated with another of the peripheral co-processors using a direct memory access operation that does not involve a CPU.

Abstract: A system and method processes graphics data for remote display. A graphics processing system including a plurality of graphics processing devices is coupled to a host system that includes a host graphics processor and a display device that is remote relative to the graphics processing system. Graphics processing performance may be scaled by distributing processing between the plurality of graphics processing devices and the host graphics processor such that each of the plurality of graphics processing devices and the host graphics processor produces a portion of an image. The portions are combined to produce the image, which is output by the host graphics processor to the display device.

Abstract: An application executing on a rendering computer invokes a physics function request, e.g., to model the movement and interaction of objects to be rendered. The physics function request specifies a physics function to be performed on input data. Physics function request data is formatted for transmission over a network. The physics computer receives the physics function request data and performs an associated physics function using a physics GPU to generate physics computation result data. The physics computation result data is transmitted to the rendering computer over the network. A rendering GPU renders an image using the physics computation result data.

Abstract: A bridge associated with a broadcast aperture facilitates the transfer of rendering commands and data between a processor and multiple graphics devices. The bridge receives data written by the processor to the broadcast aperture and forwards it to multiple graphics devices, eliminating the need for the processor to perform duplicative(?) write operations. During system initialization, a broadcast aperture is allocated to the bridge in address space based on an aperture size value set using a system configuration utility and stored in system configuration memory. A graphics driver activates the broadcast aperture by sending unicast aperture parameters associated with the multiple graphics devices to the bridge via a bridge driver. Upon activating the broadcast aperture, multiple graphics devices can be operated in parallel to improve rendering performance. Parallel rendering techniques include split-frame, alternate frame, and combined split- and alternate frame rendering.

Abstract: In a multi-processor, multi-memory system, a technique designates portions of a local memory as being regions to be shadowed. A shadow control unit detects write operations to those regions designated for shadowing. The shadow control unit then executes a cloning of a write operation designated for a local memory region to be shadowed and provides the cloned data to a memory space in system memory which corresponds to the local memory region which is being shadowed.

Abstract: Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback data indicating completion of the rendering. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the display area is re-partitioned to increase a size of the portion assigned to the less heavily loaded processor and to decrease a size of the portion assigned to the more heavily loaded processor.

Abstract: Systems and methods for providing on-demand memory management. In response to a mapping request from a device driver or other program, a first portion of the memory is mapped to one or more virtual addresses in a first region of a virtual memory space so that it can be directly accessed by the CPU. In response to an unmapping request the first portion of the memory is unmapped. Mapping and unmapping requests may be made at any time.

Abstract: Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.

Abstract: A CPU selectively programs one or more graphics devices by writing a control command to the command buffer that designates a subset of graphics devices to execute subsequent commands. Graphics devices not designated by the control command will ignore the subsequent commands until re-enabled by the CPU. The non-designated graphics devices will continue to read from the command buffer to maintain synchronization. Subsequent control commands can designate different subsets of graphics devices to execute further subsequent commands. Graphics devices include graphics processing units and graphics coprocessors. A unique identifier is associated with each of the graphics devices. The control command designates a subset of graphics devices according to their respective unique identifiers. The control command includes a number of bits. Each bit is associated with one of the unique identifiers and designates the inclusion of one of the graphics devices in the first subset of graphics devices.

Abstract: Systems and methods for private addressing in a multi-processor graphics processing subsystem having a number of memories and a number of graphics processors. Each of the memories includes a number of addressable storage locations, and storage locations in different memories may share a common global address. Storage locations are uniquely identifiable by private addresses internal to the graphics processing subsystem. One of the graphics processors is able to access a location in a particular memory by referencing its private address.

Abstract: A method of self-programming a graphics processing unit (GPU) includes receiving a blit instruction defining a blit operation and storing a first control value in a control register, which determines the behavior of the GPU, using the blit operation. The blit instruction is read by the GPU from a command buffer asynchronously with the CPU. The blit operation is applied to a second control value to determine the first control value. The second control value can be stored in a memory, such as a second control register or a table of control values accessed by an index value. In one application, the second control value is a starting memory address for a display buffer, while in another application, second control value is a clip plane distance. The blit operation can include a copy operation, a colorkey operation, a logic operation, and/or a pattern copy operation on the first control value.