Patents by Inventor Frank Roberts

Frank Roberts has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984388
    Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: May 14, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Jay A. Yoder, Dennis Lee Conner, Frank Robert Cervantes, Andrew Celaya
  • Patent number: 11954851
    Abstract: A diagnostic system performs disease diagnostic tests using at least an optical property modifying device and a mobile device. A user provides a biological sample from a patient to the optical property modifying device that reacts with a reagent in one or more reaction chambers of the device. The user captures one or more images of the one or more reaction chambers using an optical sensor of the mobile device. The diagnostic system can determine a quality level of the images based on factors such as skew, scale, focusing, shadowing, or white-balancing. Based on an analysis of the captured image, the diagnostic system can determine a test result of a disease diagnostic test for the patient. The diagnostic system may communicate the test result, as well as instructions for the disease diagnostic test, to the user via the mobile device.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: April 9, 2024
    Assignee: Pfizer Inc.
    Inventors: Ivan Krastev Dimov, Frank B. Myers, III, John Robert Waldeisen, Debkishore Mitra
  • Publication number: 20240113076
    Abstract: Techniques are provided for intra-bonding multiple semiconductor integrated circuit chips to form multi-chip package structures. For example, a device comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first overlap region which comprises a first array of metallic contacts. The second semiconductor die comprises a second overlap region which comprises a second array of metallic contacts. The first overlap region and the second overlap region are overlapped and bonded together with the first array of metallic contacts aligned to the second array of metallic contacts, and with the first semiconductor die and the second semiconductor die disposed laterally adjacent to each other.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Inventor: Frank Robert Libsch
  • Patent number: 11944696
    Abstract: A detergent product containing one or more active agents is provided.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 2, 2024
    Assignee: The Procter & Gamble Company
    Inventors: Mark Robert Sivik, Gregory Charles Gordon, Frank William Denome, Alyssandrea Hope Hamad-Ebrahimpour, Stephen Joseph Hodson, Brian Patrick Croll, John Gerhard Michael, Andreas Josef Dreher, Paul Dennis Trokhan
  • Publication number: 20240079001
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a prediction of an audio signal. One of the methods includes receiving a request to generate an audio signal conditioned on an input; processing the input using an embedding neural network to map the input to one or more embedding tokens; generating a semantic representation of the audio signal; generating, using one or more generative neural networks and conditioned on at least the semantic representation and the embedding tokens, an acoustic representation of the audio signal; and processing at least the acoustic representation using a decoder neural network to generate the prediction of the audio signal.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 7, 2024
    Inventors: Andrea Agostinelli, Timo Immanuel Denk, Antoine Caillon, Neil Zeghidour, Jesse Engel, Mauro Verzetti, Christian Frank, Zalán Borsos, Matthew Sharifi, Adam Joseph Roberts
  • Patent number: 11915689
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a prediction of an audio signal. One of the methods includes receiving a request to generate an audio signal conditioned on an input; processing the input using an embedding neural network to map the input to one or more embedding tokens; generating a semantic representation of the audio signal; generating, using one or more generative neural networks and conditioned on at least the semantic representation and the embedding tokens, an acoustic representation of the audio signal; and processing at least the acoustic representation using a decoder neural network to generate the prediction of the audio signal.
    Type: Grant
    Filed: September 7, 2023
    Date of Patent: February 27, 2024
    Assignee: Google LLC
    Inventors: Andrea Agostinelli, Timo Immanuel Denk, Antoine Caillon, Neil Zeghidour, Jesse Engel, Mauro Verzetti, Christian Frank, Zalán Borsos, Matthew Sharifi, Adam Joseph Roberts, Marco Tagliasacchi
  • Patent number: 11911688
    Abstract: A game employing user-modifiable game components, such as cards in a collectable card game, employs various features to provide user-modifiability, including sleeves, transparent cards, stickers, and other elements. Electronic versions of the game and various other features are included, including tracking of history associated with such components.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 27, 2024
    Assignee: WIZARDS OF THE COAST LLC
    Inventors: Frank Gilson, Cormac Russell, Paul Sottosanti, Randy Buehler, Ramon Arjona, Karl Robert Gutschera, Brandon Anthony Bozzi, Aaron Joel Forsythe
  • Publication number: 20240053244
    Abstract: A capacitive probe structure is presented including two or more microfluidic channels defined within a plurality of dielectric layers disposed over a substrate, and a plurality of probes extending through the plurality of dielectric layers such that several probes of the plurality of probes extend to the two or more microfluidic channels to measure at least particle concentrations and particle flow within the two or more microfluidic channels. The plurality of probes are physically and electrically isolated from each other by the plurality of dielectric layers. The plurality of probes further measure a dielectric constant change for conducting and non-conducting liquids and gasses within the two or more microfluidic channels.
    Type: Application
    Filed: August 9, 2022
    Publication date: February 15, 2024
    Inventors: Frank Robert Libsch, VENKAT K. BALAGURUSAMY
  • Publication number: 20230317694
    Abstract: A device and associated method include using an optical element (OE) for electrical and optical communications on the device. A substrate includes a wiring layer with an optically transparent path which allows optical signals to pass therethrough. An optical coupling layer is coupled to the wiring layer, and the optical coupling layer includes at least one micro-lens for focusing or collimating the optical signals through the transparent path. An OE is coupled to the wiring layer, and the OE is positioned in optical alignment with the optically transparent path for communicating optical signals. One or more semiconductor chips can be communicatively coupled to an OE for controlling the OE.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Frank Robert Libsch, Kamal K. Sikka, Arvind Kumar
  • Publication number: 20230314701
    Abstract: A bridge chip of an IC packaging structure includes E/O and O/E converters and a first wiring pattern interconnecting the converters to host chips and a second wiring pattern electrically connected to the host chips. An optical interface outputs the optical signals from a backside surface of the bridge chip. The optical interface receives optical signals through the backside surface. Electrical through links connected to the second wiring pattern output electrical signals generated by the host chips through the backside surface of the bridge chip. The packaging structure includes substrate with a trench provided in the top surface of the substrate and the bridge chip disposed in the trench. The host chips are directly connected to the top surface of the bridge chip and the top surface of the substrate. Optical signals are output from the packaging structure through an opening in the bottom surface of the substrate.
    Type: Application
    Filed: April 4, 2022
    Publication date: October 5, 2023
    Inventors: Frank Robert Libsch, Kamal K. Sikka, Arvind Kumar
  • Publication number: 20230317576
    Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.
    Type: Application
    Filed: June 6, 2023
    Publication date: October 5, 2023
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen ST. GERMAIN, Jay A. YODER, Dennis Lee CONNER, Frank Robert CERVANTES, Andrew CELAYA
  • Patent number: 11755276
    Abstract: Systems and processes for operating an intelligent automated assistant are provided. In one example, a user request for a media item is received. Based on the user request, at least one media item and a description of the at least one media item are identified. A confidence level is obtained that an identified media item of the at least one media item corresponds to the requested media item. In accordance with a determination that the confidence level exceeds a first confidence threshold, a length of the identified description is reduced to obtain a modified description and the modified description of the identified media item is provided in a first spoken response.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: September 12, 2023
    Assignee: Apple Inc.
    Inventors: Andrew James Sinesio, Patrick L. Coffman, Frank-Robert Kline, III, Sara E. Kufeldt, Robert Macrae, Kranti K. Parisa, Ankur Goyal
  • Patent number: 11710686
    Abstract: Methods of forming semiconductor packages include providing a lead frame having leads and no tie-bars. Tape is attached to the lead frame and one or more semiconductor die are coupled therewith. Electrical contacts of the die are interconnected with the leads using electrical connectors. An encapsulated assembly is formed by at least partially encapsulating the die and electrical connectors. The assembly is singulated to form a semiconductor package. The tape is detached from the package or encapsulated assembly. One or more die attach flags may be attached to the tape and the die may be attached thereto. Semiconductor packages formed using the methods include one or more semiconductor die at least partially encapsulated, pins exposed through the encapsulant, electrical connectors within the encapsulant and electrically interconnecting the pins with electrical contacts of the die, and no tie-bars coupling the die with the pins. Packages may also include die attach flags.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: July 25, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Stephen St. Germain, Jay A. Yoder, Dennis Lee Conner, Frank Robert Cervantes, Andrew Celaya
  • Publication number: 20230116053
    Abstract: Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.
    Type: Application
    Filed: September 29, 2021
    Publication date: April 13, 2023
    Inventors: Devendra K. Sadana, Ning Li, Ghavam G. Shahidi, Frank Robert Libsch, Stephen W. Bedell
  • Patent number: 11621726
    Abstract: A multidimensional multilevel coding (MLC) encoder comprises a soft forward error correction (FEC) encoder receiving first bits for generating soft FEC encoded bits, a redundancy generator receiving a subset of the soft FEC encoded bits for generating redundant bits, and a hard FEC encoder receiving second bits for generating hard FEC encoded bits. Combinations of the soft FEC encoded bits, the redundant bits, and the hard FEC encoded bits form labels for mapping to a plurality of constellation points. A MLC decoder comprises a redundancy decoder, a soft FEC decoder and a hard FEC decoder. The redundancy decoder combines log-likelihood-ratios (LLR) of soft FEC encoded bits received from the MLC encoder to allow the soft FEC decoder to produce decoded bits. Decoding of hard FEC encoded bits by the hard FEC decoder is conditioned on values of the bits decoded by the soft FEC decoder.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 4, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chunpo Pan, Deyuan Chang, Frank Robert Kschischang, Yoones Hashemi Toroghi
  • Publication number: 20230084537
    Abstract: A multidimensional multilevel coding (MLC) encoder comprises a soft forward error correction (FEC) encoder receiving first bits for generating soft FEC encoded bits, a redundancy generator receiving a subset of the soft FEC encoded bits for generating redundant bits, and a hard FEC encoder receiving second bits for generating hard FEC encoded bits. Combinations of the soft FEC encoded bits, the redundant bits, and the hard FEC encoded bits form labels for mapping to a plurality of constellation points. A MLC decoder comprises a redundancy decoder, a soft FEC decoder and a hard FEC decoder. The redundancy decoder combines log-likelihood-ratios (LLR) of soft FEC encoded bits received from the MLC encoder to allow the soft FEC decoder to produce decoded bits. Decoding of hard FEC encoded bits by the hard FEC decoder is conditioned on values of the bits decoded by the soft FEC decoder.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 16, 2023
    Inventors: Chunpo PAN, Deyuan CHANG, Frank Robert KSCHISCHANG, Yoones HASHEMI TOROGHI
  • Patent number: 11476238
    Abstract: An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: October 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Frank Robert Libsch, Ali Afzali-Ardakani, James B. Hannon
  • Publication number: 20220245555
    Abstract: A system is for in-situ monitoring and recording of fish health of fish in a fish cage. The system has at least one camera housing. The camera housing is provided with a camera group having at least two cameras arranged to take synchronized pictures for digital close-range photogrammetry. The system has a central data-processing unit, the central data-processing unit being arranged to calculate a three-dimensional model of an object photographed synchronously by the at least two cameras. The data-processing unit is arranged to report the number of structures deviating from the smooth surface of the object in the three-dimensional model.
    Type: Application
    Filed: June 18, 2020
    Publication date: August 4, 2022
    Applicant: SUBC3D AS
    Inventors: Frank Robert Wiik Prytz, Bjørn Grøtting
  • Publication number: 20220157657
    Abstract: Embodiments of the invention include a method of singulating IC chips from a wafer. The method can include receiving the wafer having a substrate formed under active layers. The wafer includes a chip that includes a first portion of the active layers and a first portion of the substrate. A separation trench is formed by using an etch operation to remove a first segment of the active layers and a first segment of the substrate that are beneath a first separation channel of the wafer. The separation trench separates the first portion of the active layers from a remaining portion of the active layers; and separates the first portion of the substrate from a remaining portion of the substrate. The first IC chip is seperated from the wafer by removing a first section of the remaining portion of the substrate that is underneath the first portion of the substrate.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Cyril Cabral, JR., Frank Robert Libsch, Chitra Subramanian, Peter Jerome Sorce, Paul Alfred Lauro, John M. Papalia
  • Patent number: D1023781
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 23, 2024
    Assignee: The Procter & Gamble Company
    Inventors: Sun-Jan Alan Huang, Mark Robert Sivik, Frank William Denome, Christopher Lee Haun