Abstract: Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Abstract: This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

Abstract: A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input sample have different signs, comprises generating a first analog signal corresponding to the first input sample using a first subset of the number of cells of the digital to analog conversion circuitry with a local oscillator signal having a first polarity. The method further comprises applying a second local oscillator signal with an inverted polarity to a second subset of cells of the digital to analog conversion circuitry when a number of cells from the first subset of cells are used and selecting a number of cells from the second subset of cells to generate a second analog signal corresponding to the second input sample.

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract: A digital to analog converter (DAC) circuit to convert a digital input signal to an analog output signal, wherein the digital input signal comprises a plurality of Least Significant Bits (LSBs) and a plurality of Most Significant Bits (LSBs). The DAC circuit comprises a line decoder configured to receive the plurality of LSBs of the digital input signal and configured to generate line information based thereon. The DAC circuit further comprises a column decoder configured to receive the plurality of MSBs of the digital input signal and configured to generate column information based thereon. Further, the DAC circuit comprises one or more source cells arranged in a plurality of rows and a plurality of columns, wherein the one or more source cells are configured to be selectively activated and consequently generate an individual output signal based on the line information and the column information respectively.

Abstract: This application provides apparatus and methods for a capacitive digital-to-analog converter (CDAC) based power amplifier. In an example, a transmitter amplifier can include an input inductor, a switch having a first node coupled to the input inductor, and a control node, the amplifier configured to receive a first analog representation of an envelope signal at the first node, to receive a second analog representation of the amplitude signal from the inductor, to receive a phase signal at the control node, and to provide a first modulated signal using the phase signal, the first analog representation of the amplitude signal and the second analog representation of the amplitude signal, and a capacitive digital-to-analog converter (CDAC) configured to receive a digital representation of the amplitude signal and to provide the first analog representation of the amplitude signal.

Abstract: One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of unit cells arranged in rows and columns. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the unit cells to an output of the DAC. The number of unit cells which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.

Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

Abstract: This application provides apparatus and methods for a capacitive digital-to-analog converter (CDAC) based power amplifier. In an example, a transmitter amplifier can include an input inductor, a switch having a first node coupled to the input inductor, and a control node, the amplifier configured to receive a first analog representation of an envelope signal at the first node, to receive a second analog representation of the amplitude signal from the inductor, to receive a phase signal at the control node, and to provide a first modulated signal using the phase signal, the first analog representation of the amplitude signal and the second analog representation of the amplitude signal, and a capacitive digital-to-analog converter (CDAC) configured to receive a digital representation of the amplitude signal and to provide the first analog representation of the amplitude signal.

Abstract: Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a driving stage. The digital control stage is configured to provide a digital control signal based on digital information describing an amplitude of a digital baseband transmit signal. The driving stage is configured to provide a supply voltage for an RF amplifier (RF=radio frequency) based on the digital control signal.

Abstract: Representative implementations of devices and techniques provide a regulator having a high regulation speed and low noise across a wide frequency range. A pass through device outputs a regulated voltage based on a control signal output by an error amplifier. The control signal is boosted via a regulated boost signal.

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract: Some examples relate to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and an array of cells. Respective cells in the array comprise respective capacitors. The DAC also includes a control circuit configured to, based on the multi-bit digital input signal, selectively induce one or more corresponding capacitors to discharge current to an output terminal of the DAC.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of multiple parallel analog inputs. An input interface is arranged to organize the parallel analog inputs and an analog-to-digital converter (ADC) is arranged to sequentially convert the multiple parallel analog inputs to digital results.

Abstract: Representative implementations of devices and techniques provide a regulator having a high regulation speed and low noise across a wide frequency range. A pass through device outputs a regulated voltage based on a control signal output by an error amplifier. The control signal is boosted via a regulated boost signal.

Abstract: A pre-processing unit for a signal processor includes a pre-processing element. The pre-processing element is configured to receive data to be processed by the signal processor, to pre-process the receive data and to output the pre-processed data. The data is pre-processed based on a control signal describing an undesired signal characteristic of a supply voltage for the signal processor in order to compensate an influence of the signal characteristic of the supply voltage on the processing of the data.

Abstract: A RF digital to analog converter has a first capacitor arrangement, a first common node, and a first controller. The first capacitor arrangement has multiple switchable capacitor paths arranged in parallel. Respective switchable capacitor paths have a switchable element and a capacitor coupled in series. The first common node is connected to the multiple switchable capacitor paths. The first controller receives a baseband signal having a component, and a local oscillator (LO) signal. The first controller combines the component and the LO signal to obtain a first modulation signal. The first controller controls the multiple switchable capacitor paths of the first capacitor arrangement with the first modulation signal.