Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: An RF amplifier for amplifying a composite RF signal includes a first RF signal and a second RF signal. The amplifier includes a first amplifying stage for providing a first amplified signal a second amplifying stage for providing a second amplified signal, a third amplifying stage for providing a third amplified signal and a fourth amplifying stage for providing a fourth amplified signal, the fourth amplifying stage being arranged after the third amplifying stage. The respective amplified signals are summed up to obtain amplified RF signals.

Abstract: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width.

Abstract: This disclosure relates to monitoring and controlling a voltage characteristic of a Drain Extended Metal Oxide Semiconductor (DeMOS) transistor.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first area and a second area. The first area is stress engineered to provide enhanced mobility in a first channel that has a first width. The second area is stress engineered to provide enhanced mobility in a second channel that has a second width. The first channel and the second channel provide a combined current that is greater than a single current provided via a single channel having a single width that is substantially equal to the sum of the first width and the second width.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a first switch, a second switch, and a third switch. The first switch is configured to latch a bit in a series of bits to provide a latched bit. The second switch is configured to conduct based on the latched bit. The third switch is configured to conduct based on the latched bit and a next bit in the series of bits. The next bit follows the latched bit in the series of bits.

Abstract: The invention relates to a power-saving multibit delta-sigma converter (1) comprising: an input (2) for an analog input signal (ZA) and an output (3) for a digital output signal (ZD); a digital-to-analog converter (4) having a bit width N and serving to convert the digital output signal (ZD) to an analog feedback signal (Z3); a summing device (5) for solving the difference between the input signal (ZA) and the feedback signal (Z3); a filter (6) for filtering the difference signal (Z1); and a clocked quantizing device (7) for quantizing the filtered difference signal (Z2) into a digital output signal (ZD) with the bit width N.

Abstract: An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate having a buried oxide insulating region. A MuGFET device may be formed above the buried oxide region and coupled to a first source of reference potential. A semiconductor device may be formed above the substrate and coupled to a second source of reference potential. A coupling network may be formed to couple the MuGFET device to the semiconductor device.

Abstract: An RF amplifier for amplifying a composite RF signal includes a first RF signal and a second RF signal. The amplifier includes a first amplifying stage for providing a first amplified signal a second amplifying stage for providing a second amplified signal, a third amplifying stage for providing a third amplified signal and a fourth amplifying stage for providing a fourth amplified signal, the fourth amplifying stage being arranged after the third amplifying stage. The respective amplified signals are summed up to obtain amplified RF signals.

Abstract: A successive approximation analog/digital converter converting an analog input signal into a digital output value by means of a plurality of successive conversion cycles, comprises at least one first input for injecting an analog input signal, a controllable capacitive network which is connected downstream of the first input and which is divided into at least two capacitive subnetworks and, at least two parallel-connected and parallel-operating comparators for defining a number of comparator thresholds which corresponds to the number of parallel comparators. The comparators are respectively connected downstream of one of the capacitive subnetworks and the comparators output a corresponding number of digital intermediate signals on the basis of the comparisons in the comparators. The analog/digital converter further comprises a register set by the intermediate signals.

Abstract: The invention relates to a power-saving multibit delta-sigma converter (1) comprising: an input (2) for an analog input signal (ZA) and an output (3) for a digital output signal (ZD); a digital-to-analog converter (4) having a bit width N and serving to convert the digital output signal (ZD) to an analog feedback signal (Z3); a summing device (5) for solving the difference between the input signal (ZA) and the feedback signal (Z3); a filter (6) for filtering the difference signal (Z1); and a clocked quantizing device (7) for quantizing the filtered difference signal (Z2) into a digital output signal (ZD) with the bit width N.

Abstract: The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25?) on the basis of the actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?). The present invention likewise provides a method for digital-analog conversion.

Abstract: The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25?) on the basis of the actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?). The present invention likewise provides a method for digital-analog conversion.

Abstract: An A/D converter for converting an analog input into a binary-encoded word includes a bit-weight memory storing bit weights that include maximum, mimimum, and medium weights. During a conversion step, first and second registers store lower and upper weights, and a D/A converter converts one of the upper and lower weights into an analog bit-weighting signal. A comparison device provides a comparison result indicative of a comparison between the analog input and the analog bit-weighting signal and stores the result in a third register. A multiplexer selects the upper weight when the analog input exceeds the analog bit-weighting signal and the lower weight otherwise. A subtractor subtracts, from the bit weight of a preceding conversion step, a smaller weight that is smaller than, but closest, to the previous bit weight. An adder adds the new lower weight to the smaller weight to get a new upper bit weight.

Abstract: A successive approximation analog/digital converter converting an analog input signal into a digital output value by means of a plurality of successive conversion cycles, comprises at least one first input for injecting an analog input signal, a controllable capacitive network which is connected downstream of the first input and which is divided into at least two capacitive subnetworks and, at least two parallel-connected and parallel-operating comparators for defining a number of comparator thresholds which corresponds to the number of parallel comparators. The comparators are respectively connected downstream of one of the capacitive subnetworks and the comparators output a corresponding number of digital intermediate signals on the basis of the comparisons in the comparators. The analog/digital converter further comprises a register set by the intermediate signals.

Abstract: A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlineari

Abstract: Circuit arrangement (1) for the delay adjustment of analog-to-digital converters (4-1, . . . 4-N, 504) operating in a temporally offset manner, having at least two analog-to-digital converters (4-1, . . . 4-N, 504) each having a signal path, which receive an analog signal (VI) present at an input (2) of the circuit arrangement (1) and in each case convert it into a digital intermediate signal (Z1, . . . ZN), the analog-to-digital converters (4-1, . . . 4-N, 504) in each case being clocked by clock signals (CLK1, . . . CLKN) which have a predetermined time offset with respect to one another; having a logic circuit (7), which interconnects the digital intermediate signals (Z1, . . . ZN) for the purpose of generating a digital output signal (ZD) of the circuit arrangement (1); it being possible to set the bandwidth of the signal paths of the analog-to-digital converters (4-1, . . . 4-N, 504) in each case in such a way that a deviation of the clock signal (CLK1, . . .

Abstract: A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlineari