Patents by Inventor Fred T. Brauchler

Fred T. Brauchler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230085441
    Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package leadframe having a first die pad and a second die pad separated from the first die pad. A first semiconductor die is attached to the first die pad of the package leadframe. A second semiconductor die is attached to the second die pad of the package leadframe. A communication device is attached over the second semiconductor die. The communication device is configured to communicate wirelessly with the second semiconductor die.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Jerry Rudiak, Burton Jesse Carpenter, Fred T. Brauchler
  • Patent number: 11502068
    Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 15, 2022
    Assignee: NXP USA, INC.
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Patent number: 11462494
    Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device package includes a package substrate having a first inductive coil. A first semiconductor die is attached to a first major surface of the package substrate. The first semiconductor die includes a second inductive coil substantially aligned with the first inductive coil. A second semiconductor die is attached to the first major surface of the package substrate. A wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 4, 2022
    Assignee: NXP USA, INC.
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Publication number: 20220285330
    Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 8, 2022
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Publication number: 20220102292
    Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device package includes a package substrate having a first inductive coil. A first semiconductor die is attached to a first major surface of the package substrate. The first semiconductor die includes a second inductive coil substantially aligned with the first inductive coil. A second semiconductor die is attached to the first major surface of the package substrate. A wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Patent number: 11164826
    Abstract: A packaged integrated circuit (IC) device includes a first IC die, a first layer of adhesive on a first major surface of the first IC die, and an isolation layer over the first layer of adhesive. The isolation layer has a first major surface and a second major surface, and the second major surface of the isolation layer is between the first layer of adhesive and the first major surface. The packaged IC device also includes a first inductor coil on the first major surface of the isolation layer, a second layer of adhesive on the isolation layer, and a second IC die on the second layer of adhesive.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 2, 2021
    Assignee: NXP USA, Inc.
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Patent number: 10992346
    Abstract: An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 27, 2021
    Assignee: NXP USA, Inc.
    Inventors: Fred T. Brauchler, Qiang Li
  • Publication number: 20210066217
    Abstract: A packaged integrated circuit (IC) device includes a first IC die, a first layer of adhesive on a first major surface of the first IC die, and an isolation layer over the first layer of adhesive. The isolation layer has a first major surface and a second major surface, and the second major surface of the isolation layer is between the first layer of adhesive and the first major surface. The packaged IC device also includes a first inductor coil on the first major surface of the isolation layer, a second layer of adhesive on the isolation layer, and a second IC die on the second layer of adhesive.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Burton Jesse Carpenter, Fred T. Brauchler
  • Patent number: 10511291
    Abstract: A control system (100, 200) and method (300) are provided where a first voltage domain circuit (111) and a power switch (121) operate in a first voltage domain and where a second voltage domain circuit (109) operates in a second voltage domain, where the second voltage domain circuit includes a gate driver circuit (202) for providing a control terminal driving signal (PWM1) to drive the power switch, and also includes a watchdog communication circuit (207) for scheduling watchdog communications between the first and second voltage domain circuits to be temporally separated from noise-inducing signal transitions in the control terminal driving signal.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 17, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ibrahim S. Kandah, Fred T. Brauchler, Kim R. Gauen, David D. Putti, Vasily A. Syngaevskiy
  • Patent number: 10446476
    Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Leo M. Higgins, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, Jr., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
  • Publication number: 20190088576
    Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.
    Type: Application
    Filed: March 19, 2018
    Publication date: March 21, 2019
    Inventors: LEO M. HIGGINS, III, Fred T. Brauchler, Burton Jesse Carpenter, Jinmei Liu, Mariano Layson Ching, JR., Jinzhong Yao, Xingshou Pang, Jianhong Wang, Yadong Wei
  • Patent number: 9673809
    Abstract: In one embodiment, a control system includes a first voltage domain circuit. The first voltage domain circuit includes circuitry for operating in a first voltage domain. The control system includes a second voltage domain circuit. The second voltage domain circuit includes circuitry for operating in a second voltage domain. The second voltage domain circuit includes a driver circuit. The driver circuit for providing a control terminal driving signal to make conductive a power switch. The second voltage domain circuit includes a replication circuit, the replication circuit having an output to provide a replicated signal of the control terminal driving signal. The control system includes a galvanic isolation barrier signal path between the first voltage domain circuit and the second voltage domain circuit. The replicated signal is provided by the second voltage domain circuit to the first voltage domain circuit via the galvanic isolation barrier signal path.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Ibrahim S. Kandah, Fred T. Brauchler, Kim R. Gauen, David D. Putti
  • Patent number: 9601985
    Abstract: A segmented driver including at least one drive pin and a sense pin, a driver circuit, a comparator, and a controller. The driver circuit activates a selected drive level between the drive pins and a reference node. The comparator compares a voltage of the sense pin with a threshold voltage and provides a threshold indication when the voltage of the sense pin reaches the threshold voltage. The controller commands the driver circuit to activate a first drive level in response to an off indication, and commands the driver circuit to switch to a second, lower drive level in response to the threshold indication. The driver circuit may be implemented using low resistive current devices. Multiple drive pins may be included, each for selectively activating a corresponding drive path to adjust drive level. The threshold voltage may be set using a current source and resistor, and may be adjusted for temperature.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Ibrahim S. Kandah, Fred T. Brauchler, Steven R. Everson, Kim R. Gauen
  • Patent number: 9466413
    Abstract: Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 11, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fred T. Brauchler, John M. Pigott, Darrel R. Frear, Vivek Gupta, Randall C. Gray, Norman L. Owens, Carl E. D'Acosta
  • Patent number: 9362987
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fred T. Brauchler, Randall C. Gray
  • Patent number: 9285244
    Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 15, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: John M. Pigott, Fred T. Brauchler, William E. Edwards, Mike R. Garrard, Randall C. Gray, John M. Hall
  • Patent number: 9219028
    Abstract: An embodiment of a packaged device includes first and second package leads, a first integrated circuit (IC) die, and a sub-assembly that includes a second IC die coupled to a substrate. The first IC die has a first coil, and the second IC die has a second coil. The first and second IC die are arranged within the device so that the first and second coils are aligned with each other across a gap between the first and second IC die, and the first and second IC die are galvanically isolated from each other. The first IC die is electrically coupled to the first package lead (e.g., with a wirebond), and a substrate bond pad is electrically coupled to the second package lead (e.g., with a wirebond). The sub-assembly also may include encapsulation at least over a wirebond that electrically couples the second IC die to the substrate.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 22, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Leo M. Higgins, III, Fred T. Brauchler
  • Publication number: 20150333805
    Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Inventors: FRED T. BRAUCHLER, RANDALL C. GRAY
  • Publication number: 20150318848
    Abstract: A segmented driver including at least one drive pin and a sense pin, a driver circuit, a comparator, and a controller. The driver circuit activates a selected drive level between the drive pins and a reference node. The comparator compares a voltage of the sense pin with a threshold voltage and provides a threshold indication when the voltage of the sense pin reaches the threshold voltage. The controller commands the driver circuit to activate a first drive level in response to an off indication, and commands the driver circuit to switch to a second, lower drive level in response to the threshold indication. The driver circuit may be implemented using low resistive current devices. Multiple drive pins may be included, each for selectively activating a corresponding drive path to adjust drive level. The threshold voltage may be set using a current source and resistor, and may be adjusted for temperature.
    Type: Application
    Filed: April 30, 2014
    Publication date: November 5, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ibrahim S. Kandah, Fred T. Brauchler, Steven R. Everson, Kim R. Gauen
  • Patent number: 9172365
    Abstract: A circuit performs a method for controlling turn-off of a semiconductor switching element. The method includes determining at least one operating parameter for the semiconductor switching element during an operating cycle and determining a gate discharge current based on the at least one operating parameter. The method further includes supplying the gate discharge current to a gate of the semiconductor switching element during a subsequent operating cycle to turn off the semiconductor switching element.
    Type: Grant
    Filed: August 31, 2013
    Date of Patent: October 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ibrahim S. Kandah, Fred T. Brauchler, Steven R. Everson