Patents by Inventor Frederic Boeuf
Frederic Boeuf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947202Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.Type: GrantFiled: April 3, 2023Date of Patent: April 2, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Sébastien Cremer, Frédéric Boeuf, Stephane Monfray
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Publication number: 20230280630Abstract: A semiconductor device can be formed by etching a cavity in a first silicon layer that overlies an insulating layer, epitaxially growing a germanium or silicon-germanium layer in the cavity, epitaxially growing a second silicon layer in the cavity, etching the second silicon layer and the germanium or silicon-germanium layer to the floor of the cavity to define a first strip in the second silicon layer and a second strip in the germanium or silicon-germanium layer, selectively etching a portion of the second strip to decrease the width of the second strip, filling cavity portions arranged on either side of the first and second strips with an insulator, depositing an upper insulating layer over the first and second strips, and bonding a layer of III-V material to the upper insulating layer.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Frédéric Boeuf, Cyrille Barrera
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Publication number: 20230236446Abstract: The present disclosure relates to a method including the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.Type: ApplicationFiled: April 3, 2023Publication date: July 27, 2023Inventors: Sébastien Cremer, Frédéric Boeuf, Stephane Monfray
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Patent number: 11709315Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.Type: GrantFiled: December 2, 2021Date of Patent: July 25, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Boeuf, Charles Baudot
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Patent number: 11698296Abstract: A light sensor includes a semiconductor substrate supporting a number of pixels. Each pixel includes a photoconversion zone extending in the substrate between a front face and a back face of the substrate. An optical diffraction grating is arranged over the back face of the substrate at a position facing the photoconversion zone of the pixel. For at least two different pixels of the light sensor, the optical diffraction gratings have different pitches. Additionally, the optical grating of each pixel is surrounded by an opaque wall configured to absorb at operating wavelengths of the sensor.Type: GrantFiled: September 17, 2020Date of Patent: July 11, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Stephane Monfray, Olivier Le Neel, Frederic Boeuf
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Patent number: 11686992Abstract: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.Type: GrantFiled: September 16, 2021Date of Patent: June 27, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Frédéric Boeuf, Cyrille Barrera
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Publication number: 20230194787Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.Type: ApplicationFiled: February 10, 2023Publication date: June 22, 2023Inventors: Frédéric BOEUF, Luca Maggi
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Patent number: 11644697Abstract: The present disclosure relates to a method comprising the following steps: a) forming a waveguide from a first material, the waveguide being configured to guide an optical signal; b) forming a layer made of a second material that is electrically conductive and transparent to a wavelength of the optical signal, steps a) and b) being implemented such that the layer made of the second material is in contact with at least one of the faces of the waveguide, or is separated from the at least one of the faces by a distance of less than half, preferably less than a quarter, of the wavelength of the optical signal. The application further relates to a phase modulator, in particular obtained by such a method.Type: GrantFiled: August 7, 2020Date of Patent: May 9, 2023Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Sébastien Cremer, Frédéric Boeuf, Stephane Monfray
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Patent number: 11609378Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.Type: GrantFiled: January 31, 2022Date of Patent: March 21, 2023Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.r.l.Inventors: Frédéric Boeuf, Luca Maggi
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Publication number: 20220231483Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.Type: ApplicationFiled: April 7, 2022Publication date: July 21, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Mathias PROST, Moustafa EL KURDI, Philippe BOUCAUD, Frederic BOEUF
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Patent number: 11378827Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.Type: GrantFiled: October 29, 2020Date of Patent: July 5, 2022Assignee: STMICROELECTRONICS (CROLLES 2) SASInventors: Stephane Monfray, Frédéric Boeuf
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Publication number: 20220155519Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Frédéric Boeuf, Luca Maggi
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Patent number: 11329455Abstract: A germanium waveguide is formed from a P-type silicon substrate that is coated with a heavily-doped N-type germanium layer and a first N-type doped silicon layer. Trenches are etched into the silicon substrate to form a stack of a substrate strip, a germanium strip, and a first silicon strip. This structure is then coated with a silicon nitride layer.Type: GrantFiled: May 6, 2020Date of Patent: May 10, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Mathias Prost, Moustafa El Kurdi, Philippe Boucaud, Frederic Boeuf
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Publication number: 20220091330Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.Type: ApplicationFiled: December 2, 2021Publication date: March 24, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Frederic BOEUF, Charles BAUDOT
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Patent number: 11269141Abstract: A photonic integrated circuit chip includes vertical grating couplers defined in a first layer. Second insulating layers overlie the vertical grating coupler and an interconnection structure with metal levels is embedded in the second insulating layers. A cavity extends in depth through the second insulating layers all the way to an intermediate level between the couplers and the metal level closest to the couplers. The cavity has lateral dimensions such that the cavity is capable of receiving a block for holding an array of optical fibers intended to be optically coupled to the couplers.Type: GrantFiled: March 17, 2020Date of Patent: March 8, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (CROLLES 2) SASInventors: Frédéric Boeuf, Luca Maggi
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Patent number: 11231548Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.Type: GrantFiled: April 13, 2020Date of Patent: January 25, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Frederic Boeuf, Charles Baudot
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Publication number: 20220004076Abstract: A capacitive electro-optical modulator includes a silicon layer having a cavity having sidewalls and a floor. A germanium or silicon-germanium strip overlies the silicon layer within the cavity. A silicon strip overlies the germanium or silicon-germanium strip within the cavity. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator fills the cavity laterally adjacent the germanium or silicon-germanium strip and the silicon strip and extending between the sidewalls of the cavity. An upper insulating layer overlies the silicon strip and the insulator. A layer of III-V material overlies the upper insulating layer. The layer of III-V material formed as a third strip is arranged facing the silicon strip and separated therefrom by a portion of the upper insulating layer.Type: ApplicationFiled: September 16, 2021Publication date: January 6, 2022Inventors: Frédéric Boeuf, Cyrille Barrera
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Patent number: 11165220Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.Type: GrantFiled: October 19, 2017Date of Patent: November 2, 2021Assignees: STMicroelectronics (Crolles 2) SAS, Universite Paris-Saclay, Centre National de la Recherche ScientifiqueInventors: Anas Elbaz, Moustafa El Kurdi, Abdelhanin Aassime, Philippe Boucaud, Frederic Boeuf
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Patent number: 11150533Abstract: A capacitive electro-optical modulator includes a silicon layer, a germanium or silicon-germanium strip overlying the silicon layer, and a silicon strip overlying the germanium or silicon-germanium strip. The silicon strip is wider than the germanium or silicon-germanium strip. An insulator is laterally adjacent the germanium or silicon-germanium strip and the silicon strip and has an upper surface that is flush with an upper surface of the silicon strip. An insulating layer overlies the insulator and the silicon strip. A layer of III-V material overlies the insulating layer. The layer of III-V material is formed as a third strip arranged facing the silicon strip and separated therefrom by a portion of the insulating layer.Type: GrantFiled: July 16, 2020Date of Patent: October 19, 2021Assignee: STMicroelectronics (Crolles 2) SASInventors: Frédéric Boeuf, Cyrille Barrera
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Publication number: 20210119416Abstract: A structure includes a semiconductor support, a semiconductor region overlying the semiconductor support, a silicon nitride layer surrounding and straining the semiconductor region, and a metal foot separating the silicon nitride layer from the semiconductor support. The semiconductor region includes germanium. The semiconductor region can be a resonator of a laser or a waveguide.Type: ApplicationFiled: October 19, 2017Publication date: April 22, 2021Inventors: Anas Elbaz, Moustafa El Kurdi, Abdelhanin Aassime, Philippe Boucaud, Frederic Boeuf