Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes.

Abstract: According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes.

Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes.

Abstract: An inter-process signaling system and method support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes.

Abstract: In an embodiment, a method comprises: obtaining a virtual bus address; translating the virtual bus address to a physical address of a portion of NVM storing first data; determining that the first portion of NVM has been allocated previously; reading the first data from the first portion of NVM; determining whether writing second data to the first portion of the NVM would change one or more bits in the first data; responsive to the determining that a write operation only changes data bits in the first data from 1 to 0, writing the second data over the first data stored in the first portion of NVM; and responsive to the determining that one or more bits in the first data would be flipped from 0 to 1, reallocating the first portion of NVM to a second portion of NVM, copying the first data from the first portion of NVM to the second portion of NVM with the first data modified by the second data.

Abstract: The disclosed embodiments provide security extensions for memory (e.g., non-volatile memory) by means of address and data scrambling and differential data storage to minimize exposure to side channel attacks and obfuscate the stored data. The scrambling function maximizes reverse engineering costs when recovering sequences of secret keys.

Abstract: The disclosed embodiments provide a mechanism to support implementation of semaphores or messaging signals between masters in a multi-master system, or between tasks in a single master system. A semaphore flag register contains one or more bits indicating whether resources are free or busy. The register is aliased to allow atomic read-and-clear of individual bits in the register. Masters poll the status of a resource until the resource reads as free. Alternatively, interrupts or events per master can be implemented to indicate availability of a resource.

Abstract: A circuit includes a pulse generator coupled to a switch mode power supply. The switch mode power supply includes a switching component configured for transferring a charge to an energy storage component in response to pulses provided by the pulse generator. A pulse counter is coupled to the pulse generator or the switching component and configured to count pulses over a time period and thereby generate a pulse count. A converter coupled to the pulse counter is configured to generate a power measurement for the time period based on the pulse count. If the switch mode power supply has different modes of operation, a different counter may be used for each mode.

Abstract: Systems, methods and computer-readable mediums are disclosed for providing secure access in a microcontroller system. In some implementations, a microcontroller system comprises a system bus and a secure central processing unit (CPU) coupled to the system bus. The secure CPU is configured to provide secure access to the system bus. A non-secure CPU is also coupled to the system bus and is configured to provide non-secure access to the system bus. A non-secure memory is coupled to the system bus and is configured to allow the secure CPU and the non-secure CPU to exchange data and communicate with each other. A peripheral access controller (PAC) is coupled to the system bus and configured to enable secure access to a peripheral by the secure CPU while disabling non-secure access to the peripheral based upon a non-secure state of the non-secure CPU.

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A flexible-width peripheral register mapping is disclosed for accessing peripheral registers on a peripheral bus.

Abstract: Implementations are disclosed for a centralized peripheral access controller (PAC) that is configured to protect one or more peripheral components in a system. In some implementations, the PAC stores data that can be set or cleared by software. The data corresponds to an output signal of the PAC that is routed to a corresponding peripheral component. When the data indicates that the peripheral is “unlocked” the PAC will allow write transfers to registers in the peripheral component. When the data indicates that the peripheral component is “locked” the PAC will refuse write transfers to registers in the peripheral component and terminate with an error.

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system.

Abstract: A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.