Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.

Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.

Abstract: A cell structure of a memory device includes an upper electrode structure separated from a metal line above the cell structure by a combination of one or more layers including an isolation layer. The cell structure may be patterned using a metal line below the cell structure as an etch-stop layer. Relative to other techniques that include patterning the cell structure using a silicon carbide layer located over the metal line below the cell structure as an etch-stop layer, the techniques described herein may reduce an overall height of the memory structure. Additionally, or alternatively, the techniques may maintain or increase an isolation distance between the metal line above the cell structure and the upper electrode structure. In this way, a likelihood of shorting between the metal line above the cell structure and the upper electrode structure is reduced to improve a performance and/or a reliability of the memory device.

Abstract: A memory device, a memory integrated circuit and a manufacturing method of the memory device are provided. The memory device includes a composite bottom electrode, a top electrode and a resistance variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. A sidewall of the second bottom electrode is laterally recessed from sidewalls of the first bottom electrode layer and the resistance variable layer.

Abstract: Various embodiments of the present application are directed toward an integrated chip (IC). The IC comprises a dielectric structure disposed over a substrate. A phase change material (PCM) structure is disposed over the dielectric structure. A first conductive structure and a second conductive structure are disposed over and electrically coupled to the PCM structure. A heating structure is disposed in the dielectric structure and laterally between the first conductive structure and the second conductive structure. The heating structure has a first surface and a second surface opposite the first surface. The first surface faces the PCM structure. The first surface has a first width and the second surface has a second width that is greater than the first width.

Abstract: Device structures and methods for forming the same are provided. A device structure according to the present disclosure includes a first electrode and a second electrode disposed over an etch stop layer (ESL), a first dielectric layer disposed between the first electrode and the second electrode, a phase-change material layer disposed over the first electrode, the first dielectric layer and the second electrode, an insulator layer disposed over the phase-change material layer, a metal feature disposed over the insulator layer, and a second dielectric layer disposed over the insulator layer, the first electrode, the second electrode, and the metal feature.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: A dielectric isolation layer having a planar top surface is formed over a substrate. A first electrode and a second electrode are formed over the planar top surface. An insulating matrix layer is formed around the first electrode and the second electrode. A phase change material (PCM) line is formed over the insulating matrix layer. A first end portion of the PCM line contacts a top surface of the first electrode and a second end portion of the PCM line contacts a top surface of the second electrode. A dielectric encapsulation layer is formed on sidewalls of the PCM line and over the PCM line and over a top surface of the insulating matrix layer. A heater line is formed prior to, or after, formation of the PCM line. The heater line underlies the PCM line or overlies the PCM line. A PCM switch device may be provided.

Abstract: The present disclosure relates to a memory device that includes a bottom electrode, a data storage structure overlying the bottom electrode, a top electrode overlying the data storage structure, a mask overlying the top electrode, and a sidewall spacer extending alongside the data storage structure and alongside the mask. The sidewall spacer extends to a height above an upper surface of the mask. A top electrode via (TEVA) extends through the mask to the top electrode and extends into the sidewall spacer, where a first curved portion of the sidewall spacer extends along a top surface of the mask and is spaced apart from the TEVA.

Abstract: A memory device includes a first metal structure, a magnetic tunnel junction (MTJ) structure, a second metal structure, a first spacer, and a second spacer. The MTJ structure is over the first metal structure. The second metal structure is over the MTJ structure. The first spacer is over a first sidewall of the second metal structure. The second spacer is over a second sidewall of the second metal structure. The second spacer has a top surface higher than a top surface of the first spacer.

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.

Abstract: A semiconductor structure includes a first electrode comprising a first metallic material; a memory film including at least one dielectric metal oxide material and contacting the first electrode; and a second electrode comprising a second metallic material and contacting the memory film. The memory film includes a center region having a first average atomic ratio of a passivation element to oxygen that is less than 0.01, and includes a peripheral region having a second average atomic ratio of the passivation element to oxygen that is greater than 0.05.

Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.

Abstract: An embodiment phase-change memory device includes a first electrode formed over an interconnect layer, a phase-change memory element formed over the first electrode, a second electrode formed over the phase-change memory element, and an oxygen-free spacer layer formed over sidewalls of the phase-change memory element. The phase-change memory element may include a germanium-antimony-tellurium alloy or an aluminum-antimony alloy. The phase-change memory device may include a carbon layer, configured as a heater element, formed between the first electrode and the phase-change memory element. The oxygen-free spacer layer may include SiN, SiC, or SiCN and may further include chlorine, fluorine, argon, chlorine and argon, fluorine and argon, or a mixture of chlorine, fluorine, and argon. The oxygen-free spacer layer may further include a composition that varies with position within the oxygen-free spacer layer.

Abstract: A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: A semiconductor memory structure includes a memory cell, an encapsulation layer over a sidewall of the memory cell, and a nucleation layer between the sidewall of the memory cell and the encapsulation layer. The memory cell includes a top electrode, a bottom electrode and a data-storage element sandwiched between the bottom electrode and the top electrode. The nucleation layer includes metal oxide.