Abstract: A detecting method for a behavior disorder event during rapid-eye-movement sleep is provided. The detecting method includes: collecting a heart rate value and a motion value of a user per epoch within a time period; generating a plurality of corresponding sleep condition values by using the motion values, to distinguish epochs into an awake period and a sleep period; transforming the motion values corresponding to the sleep period into a score according to a predetermined rule, to generate a plurality of sleep depth scores, and distinguishing the sleep period into a light sleep period and a deep sleep period by using the sleep depth scores; grouping the heart rate values corresponding to the deep sleep period as a high heart rate group and a low heart rate group; and determining, when the motion values corresponding to the high heart rate group satisfy a condition, that a behavior disorder event happens.

Abstract: A resistive memory device is provided. The resistive memory device includes a first electrode, a memory structure on the first electrode, and a second electrode on the memory structure. The memory structure includes a tubular element and a pillar element. The tubular element includes oxide. The pillar element includes oxide. The pillar element is surrounded by the tubular element. The tubular element and the pillar element include different materials.

Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.

Abstract: In a method of manufacturing a semiconductor device, a conductive pattern is formed in a surface region of a dielectric layer, a mask pattern including an opening over the conductive pattern is formed over the dielectric layer, a part of the conductive pattern is converted into a high-resistant part having a higher resistivity than the conductive pattern before the converting through the opening, and the mask pattern is removed.

Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.

Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.

Abstract: A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

Abstract: A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a. second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.

Abstract: A system for estimating BPs using a PPG signal analysis comprises an upper-arm wearable apparatus, a cuff-based BP measuring apparatus, a PPG signal receiver and analyzer, and a PPG to BP estimator and calibrator. The upper-arm wearable apparatus senses modeling-used PPG waveform signals. The cuff-based BP measuring apparatus obtains real PVR waveforms and real BPs. The PPG signal receiver and analyzer is configured to process the modeling-used PPG waveform signals and derive modeling-used characteristic parameters, and have modeling-used personal information parameters. The PPG to BP estimator and calibrator is configured to calculate estimated BPs based on the modeling-based characteristic parameters and the modeling-used personal information parameters, store a calibration model which approximately fits relationship between the estimated BPs and the real BPs; and calculate modeling-used calibrated-estimated BPs using the calibration model.

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining smoothness of the waveform segments; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the waveform segments, and generating a detection result.

Abstract: A method for detecting a particular syndrome based on hemodynamic analysis that includes steps of: obtaining a piece of hemodynamic data representing a hemodynamic waveform; performing moving average (MA) filtering on the hemodynamic waveform to obtain a filtered waveform; determining troughs in order to determine waveform segments of the filtered waveform; determining systolic peaks for determining first and second portions of the waveform segments; determining smoothness of the second portions; and determining a relation between the hemodynamic waveform and a particular syndrome based on the smoothness of the second portions, and generating a detection result.

Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.

Abstract: A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

Abstract: A memory structure includes a substrate. The memory structure further includes a first transistor, wherein the first transistor is a first distance from the substrate. The memory structure further includes a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor. The memory structure further includes a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.

Abstract: A method for detecting a location of a segment of a feeding tube is provided. The feeding tube has a proximal end, a hollow tube body and a distal end, and is placed inside the body of a patient. An audio collecting component is placed on a predetermined part of the patient. The method includes steps of pumping air into the proximal end of the feeding tube, collecting sound to obtain audio data by the audio collecting component, performing audio analysis on the audio data, and determining whether a segment of the hollow tube body is at a part inside the body of the patient that corresponds with the location of the audio collecting component based on result of the audio analysis.

Abstract: An integrated circuit device includes a first bit line structure that has a horizontal portion and a vertical portion in which an upper surface of the vertical portion is exposed for making electrical contact with a contact that, in turn, is in electrical contact with a metal pattern through which operating voltages may be applied to the bit line structure.

Abstract: Provided is a stainless steel powder composition, which comprises Cr, Cu, Mn, Mo, Ni and Fe; wherein, based on a total weight of the stainless steel powder composition, a content of Cr is 20 wt% to 24 wt%, and a content of Cu is more than 0 wt% and less than or equal to 0.5 wt%, a content of Mn is more than 0 wt% and less than or equal to 2 wt%, a content of Mo is 2.25 wt% to 3 wt% and a content of Ni is 10 wt% to 15 wt%. When applying the stainless steel powder composition of the present invention to laser additive manufacturing (LAM), the produced stainless steel workpiece has enhanced tensile strength, thereby expanding the follow-up applications and increasing the commercial value.