Patents by Inventor Gabi Malka
Gabi Malka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9996127Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.Type: GrantFiled: March 12, 2014Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Omer Vikinski, Igor Yanover, Gavri Berger, Gabi Malka, Zeev Sperber
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Patent number: 9716646Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.Type: GrantFiled: July 17, 2014Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: Tsvika Kurts, Beeman C. Strong, Ofer Levy, Gabi Malka, Zeev Sperber
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Patent number: 9696997Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: January 11, 2016Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Publication number: 20160117171Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: ApplicationFiled: January 11, 2016Publication date: April 28, 2016Applicant: INTEL CORPORATIONInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Patent number: 9262163Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: December 29, 2012Date of Patent: February 16, 2016Assignee: Intel CorporationInventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Publication number: 20160020897Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.Type: ApplicationFiled: July 17, 2014Publication date: January 21, 2016Inventors: TSVIKA KURTS, BEEMAN C. STRONG, OFER LEVY, GABI MALKA, ZEEV SPERBER
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Publication number: 20150261270Abstract: A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.Type: ApplicationFiled: March 12, 2014Publication date: September 17, 2015Inventors: OMER VIKINSKI, IGOR YANOVER, GAVRI BERGER, GABI MALKA, ZEEV SPERBER
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Publication number: 20140189314Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.Type: ApplicationFiled: December 29, 2012Publication date: July 3, 2014Inventors: Tsvika Kurts, Ofer Levy, Itamar Kazachinsky, Gabi Malka, Zeev Sperber, Jason W. Brandt
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Patent number: 7365753Abstract: A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered.Type: GrantFiled: July 28, 2005Date of Patent: April 29, 2008Assignee: Intel CorporationInventors: Gabi Malka, Zeev Sperber, Yael Shenhav
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Patent number: 7202871Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.Type: GrantFiled: May 12, 2004Date of Patent: April 10, 2007Assignee: Intel CorporationInventors: Gavril Margittai, Zeev Sperber, Gabi Malka
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Patent number: 7076614Abstract: A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at least one read request is then issued consecutively to system memory via the system memory bus. After issuance of the at least one read request, at least one write request is issued consecutively to send the second data in the write back buffer to the system memory via the system memory bus. The consecutive issuance of read and write requests avoids read-to-write and write-to-read bubbles that occur when alternating read and write requests are issued to system memory.Type: GrantFiled: June 29, 2001Date of Patent: July 11, 2006Assignee: Intel CorporationInventors: Zeev Sperber, Gabi Malka, Gilad Shmueli, Shmulik Branski
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Publication number: 20050264579Abstract: A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered.Type: ApplicationFiled: July 28, 2005Publication date: December 1, 2005Inventors: Gabi Malka, Zeev Sperber, Yael Shenhav
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Patent number: 6947053Abstract: A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered.Type: GrantFiled: September 27, 2001Date of Patent: September 20, 2005Assignee: Intel CorporationInventors: Gabi Malka, Zeev Sperber, Yael Shenhav
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Patent number: 6944720Abstract: A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.Type: GrantFiled: March 27, 2003Date of Patent: September 13, 2005Assignee: Intel CorporationInventors: Zeev Sperber, Guy Peled, Doron Orenstein, Ehud Cohen, Gabi Malka
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Publication number: 20040252126Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.Type: ApplicationFiled: May 12, 2004Publication date: December 16, 2004Inventors: Gavril Margittai, Zeev Sperber, Gabi Malka
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Patent number: 6781588Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.Type: GrantFiled: September 28, 2001Date of Patent: August 24, 2004Assignee: Intel CorporationInventors: Gavril Margittai, Zeev Sperber, Gabi Malka
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Publication number: 20030191903Abstract: A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.Type: ApplicationFiled: March 27, 2003Publication date: October 9, 2003Inventors: Zeev Sperber, Guy Peled, Doron Orenstein, Ehud Cohen, Gabi Malka
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Patent number: 6580427Abstract: A graphics system is provided to implement compression of depth or z-data. The graphic system includes a buffer, a status table, and a read/write unit. The buffer stores depth data for multiple blocks of pixels in associated buffer entries. The status table stores status values for the entries of the buffer. The status value for a given entry indicates an access mode for the corresponding depth data according to whether the data is compressed, uncompressed or in a reference state. The read/write unit implements data accesses for a given entry responsive to the status value associated with the entry.Type: GrantFiled: June 30, 2000Date of Patent: June 17, 2003Assignee: Intel CorporationInventors: Doron Orenstein, Guy Peled, Zeev Sperber, Ehud Cohen, Gabi Malka
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Patent number: 6557083Abstract: A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.Type: GrantFiled: June 30, 2000Date of Patent: April 29, 2003Assignee: Intel CorporationInventors: Zeev Sperber, Guy Peled, Doron Orenstein, Ehud Cohen, Gabi Malka
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Publication number: 20030063092Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Gavril Margittai, Zeev Sperber, Gabi Malka