Abstract: A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered.

Abstract: A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at least one read request is then issued consecutively to system memory via the system memory bus. After issuance of the at least one read request, at least one write request is issued consecutively to send the second data in the write back buffer to the system memory via the system memory bus. The consecutive issuance of read and write requests avoids read-to-write and write-to-read bubbles that occur when alternating read and write requests are issued to system memory.