Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.

Abstract: A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect structure is completed by first removing the masking material and sacrificial substrate. Ends of the wires are coupled opposite now-formed contact structures to a board. To complete the socket, a support device is coupled to the board to hold a tested integrated circuit.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the selected prefabricated elements is customized. The probe card assembly is then built using the selected and customized elements.

Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside.

Abstract: Methods are provided for making vertical feed through electrical connection structures in a substrate or tile. The vertical feed throughs are configured to make the tile attachable and detachable as a layer between other substrates. For example, the tile with vertical feedthroughs can form an easily detachable space transformer tile in a wafer test system. The vertical feed through paths are formed with one end of each feed through hole permanently encapsulating a first electrical contact, and a second end supporting another pluggable and unpluggable electrical probe contact. Decoupling capacitors can be further plugged into holes formed in close proximity to the vertical feed through holes to increase performance of the decoupling capacitor.

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure.

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure.

Abstract: An interconnect assembly and methods for making and using the assembly. An exemplary embodiment of an aspect of the invention includes a contact element which includes a base portion adapted to be adhered to a substrate and a beam portion connected to and extending from the base portion. The beam portion is designed to have a geometry which substantially optimizes stress across the beam portion when deflected (e.g. it is triangular in shape) and is adapted to be freestanding. An exemplary embodiment of another aspect of the invention involves a method for forming a contact element. This method includes forming a base portion to adhere to a substrate of an electrical assembly and forming a beam portion connected to the base portion. The beam portion extends from the base portion and is designed to have a geometry which substantially evenly distributes stress across the beam portion when deflected and is adapted to be freestanding.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A semiconductor chip mounting component includes a support having a top surface, a bottom surface, a central portion, a peripheral portion surrounding the central portion, and a gap extending through the support structure between the top and bottom. The component includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the support structure on one side of the gap, a second end secured to the support structure on an opposite side of the gap, and a frangible section between the first and second ends. The component also includes at least one elongated bus disposed on the peripheral portion of the support structure alongside the gap, whereby each lead extends across the gap and is connected to the bus.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiments a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A semiconductor chip package assembly is mounted to contact pads on a die. A compliant interposer layer is disposed between the die and a dielectric substrate wiring layer. The contacts on the die are connected to terminals on the compliant interposer layer by means of a compliant, conductive polymer extending through apertures in the interposer layer. Compliancy in the interposer layer and in the conductive polymer permits relative movement of the terminals on the dielectric substrate wiring layer to the contacts on the die and hence relieves the shear forces caused by differential thermal expansion. The arrangement provides a compact packaged structure similar to that achieved through flip-ship bonding, but with markedly increased resistance to thermal cycling damage.

Abstract: An interconnect assembly and methods for making and using the assembly. An exemplary embodiment of an aspect of the invention includes a contact element which includes a base portion adapted to be adhered to a substrate and a beam portion connected to and extending from the base portion. The beam portion is designed to have a geometry which substantially optimizes stress across the beam portion when deflected (e.g. it is triangular in shape) and is adapted to be freestanding. An exemplary embodiment of another aspect of the invention involves a method for forming a contact element. This method includes forming a base portion to adhere to a substrate of an electrical assembly and forming a beam portion connected to the base portion. The beam portion extends from the base portion and is designed to have a geometry which substantially evenly distributes stress across the beam portion when deflected and is adapted to be freestanding.

Abstract: A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap connecting one end of the lead connection section to a bus extending alongside the gap. The frangible section is broken when the lead is engaged with the contact.

Abstract: A semiconductor chip package assembly is mounted to contact pads on a die. A compliant interposer layer is disposed between the die and a dielectric substrate wiring layer. The contacts on the die are connected to terminals on the compliant interposer layer by means of a compliant, conductive polymer extending through apertures in the interposer layer. Compliancy in the interposer layer and in the conductive polymer permits relative movement of the terminals on the dielectric substrate wiring layer to the contacts on the die and hence relieves the shear forces caused by differential thermal expansion. The arrangement provides a compact packaged structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.

Abstract: A connection component for electrically connecting a semiconductor chip to support substrate incorporates a preferably dielectric supporting structure (70) defining gaps (40). Leads extend across these gaps so that the leads are supported both sides of the gap (66, 70). The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section (72) adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact.

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.

Abstract: A semiconduct chip assembly includes a chip, terminals permanently electrically connected to the chip by flexible leads and a resilient element or elements for biasing the terminals away from the chip. The chip is permanently engaged with a substrate having contact pads so that the terminals are disposed between the chip and the substrate and the terminals engage the contact pads under the influence of the force applied by the resilient element. The terminals typically are provided on a flexible sheet-like dielectric interposer and the resilient element is disposed between the interposer and the chip. The assembly of the chip and the terminals can be tested prior to engagement with the substrate. Because engagement of this assembly with the substrate does not involve soldering or other complex bonding processes, it is reliable. The assembly can be extremely compact and may occupy an area only slightly larger than the area of the chip itself.