Abstract: A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Abstract: Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes transmitting bits modulated with a first predefined sequence of a plurality of predefined sequences by a first medical transceiver. The first predefined sequence is detected by a second medical transceiver when the second medical transceiver enters into an active state. A predetermined action is preformed if the first predefined sequence is detected.

Abstract: Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes detecting the predefined sequence by a second medical transceiver. The method also includes performing predetermined action if the predefined sequence is detected. In one example, the predetermined action includes determining presence of a signal.

Abstract: A first phasor associated with an electronic signal and a delta phasor associated with a cyclic rate of the electronic signal are multiplied to produce a second phasor. To compensate for any deviation in the magnitude of the second phasor, a real and imaginary correction factor are determined and added to the second phasor. The imaginary and real correction factors can be determined by first calculating the sum and difference of the real and imaginary portions of the first phasor respectively. The sum and difference are then scaled by performing simple shift-operations to produce the real and imaginary correction factors. The corrected second phasor is then used to update the electronic signal, which in turn can be used to produce another signal, such as a communication signal.

Abstract: Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal up to a desired power (or the signal strength of the received signal) are determined for each antenna by examining the non-payload portion (e.g., preamble) of the packet. The antenna with the best SNR is then chosen based on the rule given. In an embodiment, the correlation value is determined based on the Barker Sequence employed for each bit in the preamble. The selection may be performed for each data packet, thereby using the antenna receiving the signal most conducive to recovery of the data bits (including payload) in each data packet.

Abstract: A first phasor associated with an electronic signal and a delta phasor associated with a cyclic rate of the electronic signal are multiplied to produce a second phasor. To compensate for any deviation in the magnitude of the second phasor, a real and imaginary correction factor are determined and added to the second phasor. The imaginary and real correction factors can be determined by first calculating the sum and difference of the real and imaginary portions of the first phasor respectively. The sum and difference are then scaled by performing simple shift-operations to produce the real and imaginary correction factors. The corrected second phasor is then used to update the electronic signal, which in turn can be used to produce another signal, such as a communication signal.

Abstract: A first phasor associated with an electronic signal and a delta phasor associated with a cyclic rate of the electronic signal are multiplied to produce a second phasor. To compensate for any deviation in the magnitude of the second phasor, a real and imaginary correction factor are determined and added to the second phasor. The imaginary and real correction factors can be determined by first calculating the sum and difference of the real and imaginary portions of the first phasor respectively. The sum and difference are then scaled by performing simple shift-operations to produce the real and imaginary correction factors. The corrected second phasor is then used to update the electronic signal, which in turn can be used to produce another signal, such as a communication signal.

Abstract: A receiver device provided according to an aspect of present invention accurately recovers streams of symbols encoded in corresponding sub-channels of a multi-carrier signal. Such a feature is attained by first recovering erroneous symbols (which are not yet corrected for carrier frequency offset) from the sub-channels, and then processing the symbols to correct for carrier frequency offset in the frequency domain.

Abstract: Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed signal IC generates an analog signal from a symbol, and transmits the analog signal to the calibrated integrated circuit. The calibrated IC determines a valid symbol corresponding to the signal level (e.g., voltage) of the received analog signal, and determines a deviation of the signal level of the received analog signal from the voltage level corresponding to the valid symbol. The deviation is deemed to represent the degree of defect of the mixed signal IC based on the assumption that the calibrated IC operates accurately. The deviation is used to either discard or qualify/accept the mixed signal IC.

Abstract: Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed signal IC generates an analog signal from a symbol, and transmits the analog signal to the calibrated integrated circuit. The calibrated IC determines a valid symbol corresponding to the signal level (e.g., voltage) of the received analog signal, and determines a deviation of the signal level of the received analog signal from the voltage level corresponding to the valid symbol. The deviation is deemed to represent the degree of defect of the mixed signal IC based on the assumption that the calibrated IC operates accurately. The deviation is used to either discard or qualify/accept the mixed signal IC.

Abstract: Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal upto a desired power (or the signal strength of the received signal) are determined for each antenna by examining the non-payload portion (e.g., preamble) of the packet. The antenna with the best SNR is then chosen based on the rule given. In an embodiment, the correlation value is determined based on the Barker Sequence employed for each bit in the preamble. The selection may be performed for each data packet, thereby using the antenna receiving the signal most conducive to recovery of the data bits (including payload) in each data packet.