Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.

Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Abstract: Disclosed are a system and method of transmitting data in a processing platform. A switch may comprise an upstream port coupled to a root device to communicate with a processing system. The switch may also comprise a plurality of downstream ports where each downstream port is adapted to be coupled to a device. Data may be transmitted between downstream ports based upon routing information for transmitting data from the upstream port to each of the downstream ports.

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A method and device are provided for managing a group of electrical devices, e.g., coder/decoders (codecs) in a computer system. Members of a group of electrical devices may be located on the motherboard of the computer system, or off the motherboard, such as on a riser card. An address ID module assigns a primary address to designate one of the devices as a primary device. The primary device performs certain functions that are only performed by a single device. Other devices are designated as secondary devices. A signal indicates whether a member of the group of electrical devices is located on the motherboard. If no device is located on the motherboard, the address ID module designates a primary device and secondary devices from among the devices located on the riser card. A routing module routes output signals from the devices to input pins of a controller.

Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A machine for lapping bowling balls and, thus, re-rounding, smoothing, and cleaning the balls. The machine is comprised of three concave abrasion blocks with drive motors, adjustable mounting brackets attached to an adjustable support table, a catch basin with filter to separate suspended solids from liquids, and a pump and fluid delivery tube to deliver flushing and/or cleaning liquids. The abrasion blocks are comprised of resilient concave blocks with abrasive sanding disks. The positions of all three abrasion blocks are preferably simultaneously and equally adjusted by small adjustments to the position of a top table relative to the stand that holds the pivotal motor mounts. Ramps on the rotatable table cooperate with the mounts to slightly pivot the motor mounts inward and outward from the ball, changing the orientation and distance of the abrasive blocks relative to each other and, hence, to the ball.

Abstract: A computer includes a dual mode power supply that includes a main voltage converter and a standby voltage converter. The main voltage converter generates a main operating voltage at a normal operating current. The standby voltage generator generates a standby voltage at a standby current. The power supply outputs a dual mode output that includes both the main voltage and the standby voltage. The standby current is less than the normal operating current. The computer includes a host processor, a memory array, and a wake-up device. A power management device is coupled to the host processor and receives at least the standby voltage. The dual mode output from the power supply is input to the wake-up device and the memory array to allow the computer to be placed in a power saving mode by terminating supply of the main voltage. While in the power saving mode and receiving only the standby voltage, the wake-up device can wake-up the computer.

Abstract: Apparatus and method of assisting software emulation of hardware functions in a processor. During a read cycle on an address bus, an address that is within a predetermined address range is stored in a trap register and a Type-of-Cycle bit in the trap register is set to the read state. If an Issue-SMI-on-Next-Access bit in the trap register is set to the on state, a system management interrupt is issued to the processor. During a write cycle, data on the data bus is stored in a data field of the trap register, the address is stored in the address field of the trap register and the Type-of-Cycle bit is set to the write state. A system management interrupt is issued if the Issue-SMI-on-Next-Access bit is set to the on state. Then the Issue-SMI-on-Next-Access bit is set to the off state. The Type-of-Cycle bit of the trap register is set if the system management interrupt is detected at the processor.

Abstract: A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent is granted to that bus agent for executing a transaction. A timer is started and the transaction is executed. If the timer does not expire before the transaction is completed, another request from that same bus agent is granted to the bus agent for executing an additional transaction before a subsequent arbitration event is initiated.

Abstract: An apparatus includes a first register having a first field that stores a first value that indicates a power management state of a bus. A bus regulator is coupled to the first register. The bus regulator regulates the bus according to the power management state.

Abstract: A computer system is provided with a device driver for adaptively operating a number of audio peripherals through a pair of digital audio controller and analog audio interface, in accordance with the audio functions supported by the analog audio interface, including for at least one audio function, the kind of support being provided. The analog audio interface includes one or more control registers for storing a number of functional indicators to indicate the audio functions supported, and for the at least one audio function, the support kind. The analog audio interface further includes a number of control registers for storing control information for modifying the behavior of the supported audio functions.

Abstract: A method for communicating information from a first integrated circuit (IC) to a second IC. A sync signal is transmitted between the two IC's to indicate the start of a transmission of a frame of information from the first IC to the second IC. In this case, a frame of information includes a tag slot and a plurality of data slots. The tag slot contains a series of tag bits wherein each tag bit is associated with a data slot. The value of each tag bit indicates whether its corresponding data slot contains valid or invalid data. The first IC sends the tag slot and data slots to the second IC.

Abstract: A collection buffering scheme for a computer system having agents of a pre-emptible bus and a non-pre-emptible bus. An agent of the non-pre-emptible bus, having a data width capability of N bits, when receiving a grant to write to the pre-emptible bus, writes instead to a collection buffer capable of holding a block of more than one N bit data segments. When the collection buffer is filled, the collection buffer writes the entire block of data segments over the pre-emptible bus to a CPU or memory of the computer system. Preferably, the collection buffer is filled when the block size is equal to the data width capability of the pre-emptible bus, such that a single write to the pre-emptible bus utilizes the entire capacity of pre-emptible in a given data transaction. Further, where the system has a CPU posting buffer, a system lock-up prevention negotiator is provided that drains and disables the CPU posting buffer during the data transaction.

Abstract: A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.

Abstract: An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

Abstract: A method and apparatus for dynamically tuning a shared resource's bandwidth utilization, which enables system I/O software to control the length of burst accesses of a shared resource by peripheral components coupled to a peripheral component bus. The present mechanism enables the system I/O software to conduct empirical tests of bandwidth utilization by bus masters accessing the shared resource over the peripheral component bus. Based upon the empirical tests, the system I/O software can tune bandwidth utilization to attain a balance between peripheral component bus performance, and host bus performance.

Abstract: A method and apparatus for reducing cost and complexity of devices in a bus bridge circuit by dividing address and data paths between separate devices to reduce pin count, and by looping back "bridged" configuration data to access configuration registers. The host bridge circuit "bridges" all I/O accesses received over a host bus directly to a peripheral component bus without any decoding. The CDC is both initiator and target on the peripheral component bus for I/O access cycles generated by the host bridge circuit that are targeted for a host bridge configuration register.