Abstract: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Abstract: An electrical circuit contains volatile states that are lost without continued application of power to circuit elements to preserve their volatile states. A first power source in the circuit provides power to the volatile state circuit for holding and preserving their volatile states. A power selection circuit is coupled to the circuit elements and has a plurality of selectable modes. A first mode of operation of the power selection circuit is selected when the circuit elements are to be operated at a first power level via the first power source which constitutes a first mode of operation. A second mode of operation is selected when the volatile state circuit elements are to be operated under a condition where the first power source is inactivated, such as, for example, during a circuit backup or standby operation.

Abstract: An electrical circuit contains volatile states that are lost without continued application of power to circuit elements to preserve their volatile states. A first power source in the circuit provides power to the volatile state circuit for holding and preserving their volatile states. A power selection circuit is coupled to the circuit elements and has a plurality of selectable modes. A first mode of operation of the power selection circuit is selected when the circuit elements are to be operated at a first power level via the first power source which constitutes a first mode of operation. A second mode of operation is selected when the volatile state circuit elements are to be operated under a condition where the first power source is inactivated, such as, for example, during a circuit backup or standby operation.

Abstract: A backup volatile state retention circuit is provided with low leakage current for employment with a volatile memory circuit to store the value of the latter during power down of the volatile circuit or during power-down or inactivation of neighboring or peripheral circuits or due to the loss of power of any of these circuits. An example of such a volatile circuit is a memory circuit having volatile memory cells such as employed in dynamic memory core, in particular, a random access memory (RAM) in CMOS circuitry.

Abstract: A data communication interface for transferring at least one data bit to a host processor. The interface includes a one-wire data line, and a slave processor connected to the data line and including a pull-down circuit for varying voltage on the data line. The slave processor is passive and incapable of sampling data from the data line. The slave processor is programmed to vary voltage on the data line when the data line is energized, to signal at least one data bit.

Abstract: A battery monitoring system and method in accordance with the principles of the present invention, a capacity of interest is determined. This capacity of interest is the useful battery capacity required for an operation of interest; that is, the battery capacity at the discharge rate required for the operation of interest. The operation of interest may be a save-to-disk operation during a battery operated computer shutdown or a shutdown procedure for a personal digital assistant, for example. Given the capacity of interest, alarm settings are determined for a variety of voltage, discharge, and, optionally, temperature conditions. The trip points map, or index, voltage and discharge rate information for one or more discharge rates to one or more capacities of interest.

Abstract: An analog-to-digital converter (ADC) includes storage for one or more configuration parameter values. Configuration parameter values stored in the storage locations are used by control logic to configure the ADC's conversion mechanism. The configuration values may be arranged in lists that the control logic cycles through in order to modify the configuration of the ADC's conversion mechanism. The control logic may change from one list, or series of lists, to another in order to adapt the ADC to changing circumstances. The changing circumstances may include the changing state of charge in a battery monitoring application.

Abstract: A battery monitoring system and method in accordance with the principles of the present invention, a capacity of interest is determined. This capacity of interest is the useful battery capacity required for an operation of interest; that is, the battery capacity at the discharge rate required for the operation of interest. The operation of interest may be a save-to-disk operation during a battery operated computer shutdown or a shutdown procedure for a personal digital assistant, for example. Given the capacity of interest, alarm settings are determined for a variety of voltage, discharge, and, optionally, temperature conditions. The trip points map, or index, voltage and discharge rate information for one or more discharge rates to one or more capacities of interest.

Abstract: Serial bus modules with unique multibit identifications that may be searched with multiple modules on a single bus. Modules may contain temperature history per integrated Arrhenius temperature dependent signal. Modules may be packaged as tokens or as two or three lead plastic plastic, also with the three lead packages further functionality as sensors or switches may be incorporated into the modules.

Abstract: A temperature detector comprising temperature sensing circuitry, calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a valve that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry.

Abstract: A method of communicating information between a host device and a potentially portable module device which measures thermal accumulation over time via a temperature controlled counter. The temperature controlled counter may operate using substantially Arrhenius' law. The host device communicates with the portable module via a single wire bidirectional data bus. The single wire bus and one-wire communication protocol allows data flow between a host and a plurality of devices connected to the single wire bus. The single wire bus allows for a great versatility of uses for the portable module.

Abstract: A metalization layer formed as part of a bump connection/flip chip process for a semiconductor circuit is also used to form a sense resistor or other passive components. The metalization layers normal composition can also be altered so as to change or control the value of the so formed resistor or to improve the temperature stability of the resistor. Other passive components such as capacitors or inductor can also be formed in this layer.

Abstract: A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.

Abstract: A power regulator for providing a fixed output voltage that is consistent with a reference voltage and independent of a varying power supply, includes a first input connected to a reference voltage generator; a second input adapted to be connected to a varying power supply; two outputs for connection to circuitry such as oscillators; a charge pump; and three transistors. The drain and gate of the first transistor are connected to the charge pump and the source is connected to the reference voltage generator; the gate of the first transistor is coupled to the gates of the second and third transistors; and the sources of the second and third transistors are coupled one of the two outputs.

Abstract: A temperature detector comprises temperature sensing circuitry calibration circuitry, and power regular circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation. The calibration circuitry interprets the temperature variation and outputs a value that represents the temperature. The power supply regulator circuitry coordinates power to the temperature sensing circuitry. Alternate embodiments of the temperature detector comprise temperature sensing circuitry, calibration circuitry, and resolution enhancement circuitry. The temperature sensing circuitry has an output that varies with a temperature to create a temperature variation. The calibration circuitry is coupled to receive the output that varies with temperature to create a temperature variation.

Abstract: A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port.

Abstract: A histogram generator system uses a sensor to periodically sample a value of a physical variable to produce at least one sample of the physical variable and a selector allocate each sample of the value of the physical variable into a corresponding counter of a counter array. The counter accumulates a number of occurrences of the value of the sample(s) of the physical variables.

Abstract: A nonvolatile memory, includes multiple nonvolatile registers with each nonvolatile register including memory cells, and further includes circuitry that writes information to each of the nonvolatile registers one at a time, in a rotating order to prolong the prevention of tunneling oxide breakdown.

Abstract: A digital controller comprises a register containing control bits and (b) an input node coupled to the register, wherein a first signal at the input node changes a first pattern of the control bits into (i) a second pattern of the control bits when a time interval between the first signal and an immediately preceding second signal is greater than a first time interval or (ii) into a third pattern of the control bits differing from the second pattern when the time interval is less than a second time interval which is less than the first time interval. The register is electrically coupled to a counter, which counts at a variable rate. The control bits controls the variable rate at which the counter counts. A second signal may also selectably change the second pattern of control bits to be changed to a fourth pattern of control bits or the third pattern of control bits to be changed to the fourth pattern of control bits.

Abstract: An system containing an integrated circuit having two separate potentiometers combined on a single substrate; each potentiometer having three separate output terminals, two being connected to the ends of a resistor string, and the third being a "wiper" terminal electrically connected to a point within the length of the resistor string. All three terminals of each potentiometer electrically float with respect to the other pins of the integrated circuit. Control logic is used to select the point in the resistor string where the wiper terminal is to connect. An additional control signal is used to connect an additional wiper to one of the two separate wiper terminals permitting the connection of the two resistor strings in series.