Patents by Inventor Gary V. Zanders

Gary V. Zanders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5517015
    Abstract: A communication module comprises a substantially token-shaped body with first and second electrically conductive surface areas. The first and second surface areas are electrically isolated from each other and circuitry is positioned in the cavity within the substantially token-shaped body, and has connections to said first and second areas. The substantially token-shaped body has a perimeter around it. The first and second electrically conductive surface areas form a substantial portion of the substantially token-shaped body. The first and second electrically conductive surface areas form a cavity. One of the surface areas forming a flange around the perimeter of the substantially token-shaped body. The flange preferably resides in one geometric plane. The circuitry provides for the receipt and transmission of digital signals that are determined as voltage differences between said first and second areas.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: May 14, 1996
    Assignee: Dallas Semiconductor Corporation
    Inventors: Stephen M. Curry, Michael L. Bolan, Kevin E. Deierling, William L. Payne, II, Hal Kurkowski, Donald R. Dias, Gary V. Zanders, Robert D. Lee, Guenter H. Lehmann
  • Patent number: 5517470
    Abstract: A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: May 14, 1996
    Assignee: Dallas Semiconductor Corporation
    Inventors: Gary V. Zanders, Francis A. Scherpenberg, Kevin E. Deierling
  • Patent number: 5513235
    Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: April 30, 1996
    Assignee: Dallas Semiconductor Corporation
    Inventors: James M. Douglass, Gary V. Zanders, Robert D. Lee
  • Patent number: 5388134
    Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: February 7, 1995
    Assignee: Dallas Semiconductor Corporation
    Inventors: James M. Douglass, Gary V. Zanders, Robert D. Lee
  • Patent number: 5297056
    Abstract: A digital potentiometer, in which the three terminals of the potentiometer are all free-floating. The position of the wiper is selected by a control signal received on a serial port. A change is made in the effective position of the wiper until the reset-bar signal goes low. Thus, the value of the potentiometer can be directly changed to any desired value, without intermediate incrementing steps. Moreover, this control arrangement allows multiple such potentiometers to share the same serial control bus, in a "daisy chain" configuration. This has the advantage that all of the potentiometers on the serial control bus will change their values at the same time. (This is advantageous, for example, in systems where such potentiometers are used to set the gain characteristics of multiple op amps.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: March 22, 1994
    Assignee: Dallas Semiconductor Corp.
    Inventors: Robert D. Lee, Gary V. Zanders
  • Patent number: 5258721
    Abstract: A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.
    Type: Grant
    Filed: August 27, 1990
    Date of Patent: November 2, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Gary V. Zanders
  • Patent number: 5243535
    Abstract: An integrated circuit containing two digital potentiometers with each potentiometer including a passive resistor string with tap points. Tap point selection is programmed through a three-wire serial port. An output multiplexing the selected tap points permits tying the two potentiometers in series to form a single potentiometer of twice the size.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: September 7, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventors: Michael L. Bolan, Robert D. Lee, Gary V. Zanders
  • Patent number: 5218225
    Abstract: A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: June 8, 1993
    Assignee: Dallas Semiconductor Corp.
    Inventor: Gary V. Zanders
  • Patent number: 5111069
    Abstract: An integrated circuit which provides multiple independently accessible low-on-state-resistance switches, using conventional CMOS technology. Charge pumping is used to boost the gate voltage to lower the on-state resistance. The surface of the chip consists primarily of a few very large path transistors. This chip is perferably combined with a power management chip which provides logic outputs, and the large PMOS switches are used for controlling the power supply to various other chips, such as SRAMs.
    Type: Grant
    Filed: March 27, 1991
    Date of Patent: May 5, 1992
    Assignee: Dallas Semiconductor Corporation
    Inventors: Kevin E. Deierling, Gary V. Zanders
  • Patent number: 5047663
    Abstract: An integrated circuit which includes switching logic to select its negative power supply voltage from the more negative of two signals (preferably ground and an input signal). Special MOS clamp diodes are used to prevent sharp transients from collapsing the voltage drop of the internal power supply lines (and so disabling the chip).
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: September 10, 1991
    Assignee: Dallas Semiconductor Corporation
    Inventors: Robert D. Lee, Gary V. Zanders
  • Patent number: 5032742
    Abstract: An integrated circuit which, for ESD protection at an input pad, uses a split series resistor, with two clamping diodes of different types. By splitting up the series resistance in this fashion, some impedance is provided before the first hard diode, without causing an excessive total impedance. When a positive-going transient appears at the pad, the current is limited only by a moderate impedance (which saves area); when a negative-going transient appears, the current is limited by a much higher impedance (which allows a lower leakage current to be achieved).
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: July 16, 1991
    Assignee: Dallas Semiconductor Corporation
    Inventor: Gary V. Zanders
  • Patent number: 5003362
    Abstract: An integrated circuit which includes a series resistor in the well tie. This resistor permits the wall to be used for clamping, without large current consumption due to the parastic bipolar device in the well.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: March 26, 1991
    Assignee: Dallas Semiconductor Corporation
    Inventors: Robert D. Lee, Gary V. Zanders
  • Patent number: 4996453
    Abstract: An integrated circuit which provides a low-power RS232 interface (or other serial interface). The integrated circuit receives separate power supply inputs for its own logic and for driving the serial line. Even if one of the power supply inputs fails, protection circuitry clamps floating nodes in the logic elements, and thereby avoids excessive current drain which might otherwise occur.
    Type: Grant
    Filed: July 28, 1989
    Date of Patent: February 26, 1991
    Assignee: Dallas Semiconductor
    Inventors: Gary V. Zanders, Robert D. Lee