Abstract: The present invention relates to an OTP memory device, a method for operating the OTP memory device and a method for fabricating the OTP memory device. In the OTP memory device, a PN junction is formed between a source-side LDD region and a source region in each OTP memory cell. During programming of the OTP memory cell, the PN junction is broken down, providing one-time programmability. Moreover, its circuit layout is simple, helping to achieve a reduced chip area and lower cost. In the method for fabricating the OTP memory device, OTP memory cells in the OTP memory device and MOS transistors are simultaneously formed on surface regions of a semiconductor substrate, reducing fabrication complexity and cost of the OTP memory device and making it suitable for mass production.

Abstract: A split-gate non-volatile memory, fabrication and control methods thereof are disclosed by the present application. The split-gate non-volatile memory includes at least one memory cell. Each memory cell includes: a drain region and an N-type doped source region, both formed in the semiconductor substrate; and a stacked gate, first spacers, a select gate and second spacers, all formed between the N-type doped source region and the drain region. The drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The memory cell is advantageous in the prevention of erroneous data determination caused by over-erase, a low programming current and a high reading current. Further, the split-gate structure will not lead to a significant increase in the memory cell's area, enhancing overall performance of the split-gate non-volatile memory.

Abstract: A non-volatile memory and fabrication method thereof are disclosed. The non-volatile memory includes at least one 2T memory cell. Each 2T memory cell includes a semiconductor substrate, a first stacked gate and a second stacked gate formed on the semiconductor substrate, and a drain region, a common source/drain region and a source region formed in the semiconductor substrate. The source region and the common source/drain region are both N-type doped, and the drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The 2T memory cell is capable of preventing erroneous data determination caused by over erase and has both a low programming current and a high reading current, which improves the performance of the non-volatile memory.

Abstract: A one-time programmable memory unit cell includes a substrate comprising thereon a first active area and a second active area isolated from the first active area, a read select transistor disposed on the first active area, a data storage transistor disposed on the first active area and serially connected to the read select transistor, and a program select transistor disposed on the second active area. During read operation, the state “1” bit current is the transistor “on” current, while the state “0” bit current is the transistor “off” current.

Abstract: A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.

Abstract: A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

Abstract: A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.

Abstract: A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Abstract: A semiconductor memory device includes at least an OTP cell having a transistor and a PN junction diode. The OTP cell further includes a substrate having a first conductivity type, and a source and a drain in the substrate. The source includes a source doping region having the first conductivity type. The drain includes a drain doping region having a second conductivity type opposite to the first conductivity type. A gate is disposed on the substrate between the source and the drain. The source further includes a pocket doping region having the second conductivity type under the gate. The pocket doping region and the source doping region constitute the PN junction diode.

Abstract: A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Abstract: A semiconductor device and methods thereof are disclosed. The proposed semiconductor device includes at least a unit cell wherein the unit cell includes a select transistor, and half of a ground-gate transistor electrically connected to the select transistor, and including a central conductive gate electrode region, two side conductive spacer regions and a gate dielectric layer, wherein a first and a second thicknesses of the gate dielectric layer underneath the two side conductive spacer regions are thinner than a third thickness of the gate dielectric layer underneath the central conductive gate electrode region.

Abstract: A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Abstract: A semiconductor device and methods thereof are disclosed. The proposed semiconductor device includes at least a unit cell wherein the unit cell includes a select transistor, and half of a ground-gate transistor electrically connected to the select transistor, and including a central conductive gate electrode region, two side conductive spacer regions and a gate dielectric layer, wherein a first and a second thicknesses of the gate dielectric layer underneath the two side conductive spacer regions are thinner than a third thickness of the gate dielectric layer underneath the central conductive gate electrode region.

Abstract: A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A semiconductor memory device includes a substrate; a film stack on the substrate; a silicon device layer on the film stack; and a trench with corrugated sidewall surface extending into the silicon device layer, the film stack, and the substrate. A trench capacitor is located in the trench. The trench capacitor includes an inner electrode and an outer electrode with a node dielectric layer therebetween. The node dielectric layer is in direct with the film stack and the bulk semiconductor substrate. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the trench capacitor.

Abstract: A magnetic memory device includes an MTJ element between a bottom electrode layer and a top electrode layer. The MTJ element comprises a reference layer, a tunnel barrier layer and a free layer. The reference layer comprises sub-layers that protrude beyond a sidewall of the tunnel barrier layer. The tunnel barrier layer protrudes beyond a sidewall of one of sub-layers of the free layer. Sidewall spacers are disposed to respectively cover a sidewall of the top electrode layer, sidewalls of the sub-layers of the free layer, a sidewall of the tunnel barrier layer, and sidewalls of the sub-layers of the reference layer. The etching of the MTJ stack and the formation of the sidewall spacers are carried out in the same HDPCVD chamber without breaking the vacuum.

Abstract: A semiconductor substrate having a gate dielectric layer and a conductive layer is provided. The conductive layer is patterned into a main gate portion. A drain region and a source region are formed on two sides of the main gate portion, respectively. By thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between a channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region are formed. A first extension gate portion and a second extension gate portion are formed on two opposite sidewalls of the main gate portion, respectively. The main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.