Abstract: A physically unclonable function (PUF) circuit includes a at least a PUF bit storage transistor. The at least a PUF bit storage transistor has a gate-to-source/drain breakdown voltage lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Abstract: A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Abstract: A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

Abstract: A semiconductor device includes a bottle-shaped capacitor cavity extends through a silicon device layer and a buried oxide layer of a substrate. The bottle-shaped capacitor cavity includes an upper portion in the silicon device layer and a widened bottom burrow in the buried oxide layer and underneath the silicon device layer. The widened bottom burrow is wider than the upper portion. A buried capacitor is disposed in the bottle-shaped capacitor cavity. The buried capacitor includes an inner electrode and an outer electrode with the capacitor dielectric layer therebetween. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode.

Abstract: A semiconductor device includes at least a one-time programmable (OTP) physically unclonable function (PUF) unit cell with the PUF unit cell coupled to a bit line and a source line and includes an encode transistor is proposed. An encode enable transistor directly couples the bit line and the source line. A path programming the encode transistor is different from a path reading the encode transistor.

Abstract: The present disclosure provides a method for fabricating split-gate non-volatile memory. The method comprises the following: 1) preparing a semiconductor substrate by forming at least one shallow trench isolation structure in the semiconductor substrate to isolate at least one active region in the semiconductor substrate; 2) forming at least one word line on the semiconductor substrate; 3) forming at least one source and at least one drain in the semiconductor substrate, and forming at least one floating gate on a sidewall of the word line on a side close to the source; 4) removing part of the word line by adopting an etching process; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming at least one metal bit line on the conductive plug.

Abstract: A semiconductor device including at least an OTP unit cell is disclosed. The OTP unit cell includes a read select transistor, a data storage transistor serially connected to the read select transistor, and a program select transistor. The drain of the program select transistor is electrically coupled to the gate of the data storage transistor. The programming path for programming the three-transistor unit cell is different from the reading path for reading the OTP unit cell.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. A floating gate structure of the non-volatile memory is located on one side of a word line structure, and includes a second gate dielectric layer and a second conductive layer in sequence from bottom to top. The second conductive layer has a first sharp portion, a second sharp portion, and a sharp depression portion located between the two sharp portions. An erasing gate structure is located above the floating gate structure, and includes a tunneling dielectric layer and a third conductive layer in sequence from bottom to top. The tunneling dielectric layer covers tip parts of the first and second sharp portions, and is filled into the sharp depression portion. The third conductive layer has a third sharp portion at a position corresponding to the sharp depression portion.

Abstract: A semiconductor device includes a substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer. At least one capacitor cavity with corrugated sidewall surface is disposed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is provided in the at least one capacitor cavity. The at least one buried capacitor includes an inner electrode and an outer electrode with a capacitor dielectric layer therebetween.

Abstract: A semiconductor device includes a bottle-shaped capacitor cavity extends through a silicon device layer and a buried oxide layer of a substrate. The bottle-shaped capacitor cavity includes an upper portion in the silicon device layer and a widened bottom burrow in the buried oxide layer and underneath the silicon device layer. The widened bottom burrow is wider than the upper portion. A buried capacitor is disposed in the bottle-shaped capacitor cavity. The buried capacitor includes an inner electrode and an outer electrode with the capacitor dielectric layer therebetween. A transistor is disposed on the substrate. The transistor includes a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode.

Abstract: A magnetic memory device includes an MTJ element between a bottom electrode layer and a top electrode layer. The MTJ element comprises a reference layer, a tunnel barrier layer and a free layer. The reference layer comprises sub-layers that protrude beyond a sidewall of the tunnel barrier layer. The tunnel barrier layer protrudes beyond a sidewall of one of sub-layers of the free layer. Sidewall spacers are disposed to respectively cover a sidewall of the top electrode layer, sidewalls of the sub-layers of the free layer, a sidewall of the tunnel barrier layer, and sidewalls of the sub-layers of the reference layer. The etching of the MTJ stack and the formation of the sidewall spacers are carried out in the same HDPCVD chamber without breaking the vacuum.

Abstract: A method for forming a magnetic memory device is disclosed. At least one magnetic tunneling junction (MTJ) stack is formed on the substrate. The MTJ stack comprises a reference layer, a tunnel barrier layer and a free layer. A top electrode layer is formed on the MTJ stack. A patterned sacrificial layer is formed on the top electrode layer. The MTJ stack is then subjected to a MTJ patterning process in a high-density plasma chemical vapor deposition (HDPCVD) chamber, thereby sputtering off the MTJ stack not covered by the patterned sacrificial layer. During the MTJ patterning process, sidewalls of layers or sub-layers of the MTJ stack are simultaneously passivated in the HDPCVD chamber by depositing a sidewall protection layer.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) and a method for fabricating the MOSFET are disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

Abstract: A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: A current source includes a substrate, a base region of a first doping type formed in the substrate, an emitter region of a second doping type formed in the substrate and surrounding the base region, a first collector region of the second doping type formed in the base region, and at least one second collector region of the second doping type formed in the base region, wherein the emitter region includes a deep-well portion and an extending portion, the deep-well portion situated beneath the base region, the extending portion laterally surrounding the base region, the extending portion joined at its bottom to the deep-well portion, the extending portion being flush at its top with a top surface of the substrate. A method of forming the current source is also disclosed.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.