Abstract: A liquid crystal display device is provided. The liquid crystal display device includes a plurality of sub-pixels arranged in matrix, each sub-pixels is an eight domains structure; in a frame image, the data signals of the sub-pixels in two adjacent columns have opposite polarities, and in two adjacent frame images, the data signals of the same sub-pixel have opposite polarities; each two adjacent sub-pixels in a row direction are a sub-pixel group, in two adjacent sub-pixel groups, the sub-pixels in one sub-pixel group display a brightness of a first display gray scale corresponding to the sub-pixels, the sub-pixels in another sub-pixel group display a brightness of a second display gray scale corresponding to the sub-pixels; by performing the color shift compensation process on the data signals of the sub-pixels in the eight-domain structure, the color viewing angle and the viewing experience of the liquid crystal display device could be improved.

Abstract: The present disclosure relates to a programmable device. The programmable device comprises a first vertical transistor; and a second vertical transistor coupled to the first vertical transistor via a shared terminal, wherein: a first gate dielectric of the first vertical transistor has a first thickness and a second gate dielectric of the second vertical transistor has a second thickness, the first thickness being greater than the second thickness, and the second gate dielectric breaks down based on an application of a gate voltage that is lower than a first breakdown voltage of the first gate dielectric and higher than a second breakdown voltage of the second gate dielectric.

Abstract: Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

Abstract: Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.

Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

Abstract: Embodiments of the invention are directed to fabrication operations for co-integrating standard-gate (SG) and extended-gate (EG) nanosheet/nanowire transistors on the same substrate. The SG and EG nanosheet/nanowire transistors share certain fabrication operations for certain features. For example, the processes to form the bottommost channel nanosheet, the bottommost sacrificial nanosheet, and the topmost channel nanosheet are the same for SG nanosheet transistors and the EG nanosheet transistors. Because the thickness of the sacrificial nanosheet needs to be thicker for EG nanosheet transistors, a thickness of the bottommost sacrificial nanosheet is selected to accommodate the design parameters of the EG nanosheet transistor. Because the thickness of the SG and the EG channel nanosheets do not need to be different, a thickness of the bottommost channel nanosheet and the topmost channel nanosheet can be selected to accommodate the design parameters of both the SG and the EG nanosheet transistors.

Abstract: A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.

Abstract: A one-time programmable (OTP) vertical field-effect transistor (VFET) can be fabricated on the top surface of an integrated circuit (IC) substrate having a fin. A doped layer can be deposited onto the top surface to create an OTP VFET drain. A dielectric layer can be formed onto side surfaces of the fin, and a gate dielectric layer formed onto side surfaces of the dielectric layer. A metal layer formed onto side surfaces of the gate dielectric layer can create an OTP VFET gate. An electrically insulative top spacer layer can then be attached to top edges of the dielectric, the gate dielectric layer, and the metal layer. A doped structure formed onto the top surface of the fin can create an OTP VFET source. A voltage applied to a portion of the gate dielectric layer can cause dielectric breakdown, which can be used to store a data value.

Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.

Abstract: Methods of forming semiconductor devices include forming structures having an inner vertical layer and spacers on sidewalls of the inner vertical layer on a first region and a second region of a gate layer. The inner vertical layer is etched in only the first region to expose inner sidewalls of the spacers in the first region. The gate layer is etched using the remaining inner vertical layers and the spacers as a mask to form first gates in the first region and second gates in the second region. The first gates have a smaller gate length than a gate length of the second gates.

Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

Abstract: An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

Abstract: An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.

Abstract: A method is presented for integrating a first nanosheet transistor and a second nanosheet transistor on a chip. The method includes forming a first stack of alternating layers for the first gate dielectric nanosheet transistor and a second stack of alternating layers for the second gate dielectric nanosheet transistor, removing a first set of sacrificial layers of the first stack of alternating layers of the first gate dielectric nanosheet transistor and removing a first set of sacrificial layers of the second stack of alternating layers of the second gate dielectric nanosheet transistor, and removing a second set of sacrificial layers of the first stack of alternating layers. The method further includes annealing a second set of sacrificial layers to subsequently remove the second set of sacrificial layers of the second stack of alternating layers, and forming a first gate dielectric nanosheet transistor and a second gate dielectric nanosheet transistor.

Abstract: The present invention provides for a household, agricultural, coating or personal care product composition containing the crosslinked reaction product of a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2?C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r and CH2?C(R3)C(O)OXa?(C2H4O)b?(C3H6O)c?(C4H8O)d?—SO3—Y) where R3=H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a, a?, b, b?, c, c?, d and d? are 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizin