Abstract: An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in order to produce a dopant profile of the drift region in which the dopant concentration increases toward the drain. The implantation of the dopant can be performed instead before the production of the isolation area, and the later production of the isolation area (10) changes the dopant profile also in a way that the dopant concentration increases toward the drain.

Abstract: The Hall sensor semiconductor component comprises an arrangement of at least two Hall sensors (1, 2) with signal connections (11, 13, 21, 23) and supply connections (12, 14, 22, 24), and a switching network, which varies the positions of the supply connections in successive phases and connects the Hall sensors in series in each phase via the respective signal connections.

Abstract: An isolation area (10) is provided over a drift region (12) with a spacing (d) to a contact area (4) provided for a drain connection (D). The isolation area is used as an implantation mask, in order to produce a dopant profile of the drift region in which the dopant concentration increases toward the drain. The implantation of the dopant can be performed instead before the production of the isolation area, and the later production of the isolation area (10) changes the dopant profile also in a way that the dopant concentration increases toward the drain.

Abstract: A magnetic field sensor system has a plurality of magnetic field sensor elements, which each are configured to provide an individual sensor value, and of which a first portion is arranged in a first contiguous area and a second portion is arranged in a second contiguous area, and a coil wire arrangement with a first coil portion and at least a second coil portion being connected to the first coil portion, wherein the first coil portion is arranged close to the sensor elements of the first area and the second coil portion is arranged close to the sensor elements of the second area such that, if a predetermined current is applied to the coil wire arrangement, a first magnetic field component is generated at the first area and a second magnetic field component is generated at the second area being opposite to the first magnetic field component.

Abstract: A high-voltage NMOS transistor with low threshold voltage. The body doping that defines the channel region is in the form of a deep p-well. An additional shallow p-doping is arranged as a channel stopper on the transistor head. This additional shallow p-doping is produced in the semiconductor substrate at the end of the deep p-well that faces away from the channel region, and extends up to a location underneath a field oxide region that encloses the active window. The leakage current of the parasitic transistor at the transistor head is suppressed with the channel stopper.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Abstract: A Hall sensor (HS) comprises at least four sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for connecting the Hall sensor (HS) in at least two Hall sensing elements (11, 12, . . . , 44) connected together, element terminals (A, B, C, D) of the Hall sensing elements (11, 12, . . . , 44) are connected in between the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D). Each of the Hall sensing elements (11, 12, . . . , 44) is configured to provide an individual sensor value between two of its element terminals (A, B, C, D). The at least two Hall sensing elements (11, 12, . . . , 44) are distributed basically equally into two halves (B1, B2) and are connected such that a difference value is electrically formed between two of the sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) resulting from the respective individual sensor values.

Abstract: A Hall sensor comprises at least three Hall sensor elements (1, 2, . . . , 94) that respectively comprise at least three element terminals (A, B, C, D, E, F, G, H) and are interconnected in a circuit grid with a structure that is more than one-dimensional, as well as at least three sensor terminals (EXT_A, EXT_B, EXT_C, EXT_D) for contacting the Hall sensor. In this case, each sensor terminal (EXT_A, EXT_B, EXT_C, EXT_D) is connected to at least one of the Hall sensor elements (1, 2, . . . , 94) at one of its element terminals (A, B, C, D, E, F, G, H).

Abstract: On a doped well (2) for a drift section, at least two additional dielectric regions (7,9) having different thicknesses are present between a first contact region (4) for a drain and a second contact region (5) for source on the upper face (10) of the substrate (1), and the gate electrode (11) or an electric conductor, which is electrically conductively connected to the gate electrode, covers each of said additional dielectric regions at least partially.

Abstract: In order to detect light with in particular a high blue component, the inversion zone and the space charge zone of a CMOS-like structure are used. In conjunction with an at least partly transparent gate electrode, in particular a transparent conductive oxide or a patterned gate electrode, it becomes possible to absorb the short-wave component of incident light within the inversion zone and to reliably conduct away the generated charge carrier pairs to first and second contacts. During operation, a control voltage is applied to the gate electrode with a magnitude that generates a continuous inversion zone below the optionally patterned gate electrode.

Abstract: According to a method for operating a Hall sensor assembly, at least two values (I1, I2) of an input signal (I) of a Hall sensor (11) of the Hall sensor assembly (10) having different magnitudes are set and the associated values (V1, V2) of an output signal (V) of the Hall sensor (11) are determined. Furthermore, a residual offset value (k, VOFF) of the output signal (V) is determined according to the values (V1, V2) of the output signal (V) that were determined at the at least two values (I1, I2) of the input signal (I).

Abstract: The Hall sensor semiconductor component comprises an arrangement of at least two Hall sensors (1, 2) with signal connections (11, 13, 21, 23) and supply connections (12, 14, 22, 24), and a switching network, which varies the positions of the supply connections in successive phases and connects the Hall sensors in series in each phase via the respective signal connections.

Abstract: A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).

Abstract: On a doped well (2) for a drift section, at least two additional dielectric regions (7,9) having different thicknesses are present between a first contact region (4) for a drain and a second contact region (5) for source on the upper face (10) of the substrate (1), and the gate electrode (11) or an electric conductor, which is electrically conductively connected to the gate electrode, covers each of said additional dielectric regions at least partially.

Abstract: A MOSFET comprising a substrate of a semiconductor material; source/drain regions, which are arranged at a distance from each other at a surface of the substrate; a gate electrode arranged above an area of the surface of the substrate between the source/drain regions, the gate electrode being electrically insulated from the semiconductor material; at least one recess in the gate electrode, a through-contact arranged in the recess of the gate electrode, the through-contact being electrically insulated from the gate electrode; a terminal contact on the semiconductor material; and a terminal conductor arranged on the side of the gate electrode that faces away from the substrate, wherein the through-contact electrically connects the terminal contact to the terminal conductor.

Abstract: A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well.

Abstract: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less than 50 nm, with the result that a large proportion of the light quanta incident in the light incidence window can be absorbed in the lightly doped semiconductor substrate.

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Abstract: A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.

Abstract: A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed after the fabrication of the gate electrode, is replaced by a doping step, which is generated before applying the gate stack. In this way that is already a component of the remaining process sequence in the fabrication of the transistor doping can be used.