Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to selectively synchronize the broadcast frame structure at a plurality of network nodes. The described invention permits the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols, as well for the selective exclusion of nodes. This flexibility also impacts the number, the location, bandwidth, and the bit error rate (BER) of the located FSBs.

Abstract: A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.

Abstract: A system and method are provided for resynchronizing backplane link management credit counters in a packet communications switch fabric. The method comprises: at an input port card ingress port, accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between the input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; sending the generated credits to increment the counter, using the modified destination information; and, using the generated credit flow to resynchronize the credit counter.

Abstract: A system and method are provided for configuring interface bandwidths in a packet communications switch fabric. The method comprises: interfacing data links with a first plurality of traffic managers (TMs); differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs; and, communicating packets information with the TMs at a first plurality of data rates corresponding to the first plurality of subchannels. More specifically, differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs includes: differentiating a second plurality of ingress data links into a third plurality of ingress subchannels associated with a third plurality of ingress traffic managers (iTMs); and, differentiating a fourth plurality of egress data links into a fifth plurality of egress subchannels associated with a fifth plurality of egress TMs (eTMs).

Abstract: A system and method are provided for controlling packet header information in a packet communications switch fabric. The method comprises: programming the cell header overhead (OH) field definitions; accepting a packet including a plurality of cells and corresponding cell headers, each cell header including a plurality of overhead fields; defining the cell header OH fields; and, transmitting the packet. Defining the cell header OH fields includes defining cell header OH field location, position, meaning, structure, and length. In other aspects, the method comprises redefining the cell header overhead fields, once they are accepted. For example, the OH field information can be modified, relocated, or an OH field can be added to the cell header. In yet other aspects, the OH field information can be extracted and/or reformatted.

Abstract: A system and method are provided for communicating TDM communications through a packet switch fabric. The method comprises: accepting native TDM frames; converting the native TDM frames to fabric-cellified TDM frames; differentiating the cells of each frame into time slots; interleaving the frame time slots; TDM scheduling the interleaved frame time slots; and, routing the interleaved frame time slots between input port cards and output port cards on backplane data links through an intervening crossbar. TDM scheduling the interleaved frame time slots includes: an input port card ingress memory subsystem (iMS) receiving a first TDM configuration schedule including interleaved frame time slots cross-referenced to backplane transmission times; and, an output port card egress MS (eMS) receiving a second TDM configuration schedule including interleaved frame time slots cross-referenced to egress channel transmission times. Then, the routing is performed in response to the TDM schedules.

Abstract: A system and method are provided for cut-through packet routing in a packet communications switch fabric. The method comprises: accepting information packets addressed to a plurality of output port card egress ports at an input port card ingress port; routing information packets between port cards on backplane data links through an intervening crossbar; maintaining a credit counter for each port card egress destination, at the input port card; decrementing the counter in response to transmitting cells in a packet from the input port card; and, incrementing the counter in response to transmitting cells from the packet at the output port card. In some aspects of the method, accepting information includes buffering the packets in an ingress memory subsystem (iMS). Routing information includes the iMS transmitting buffered packets on a selected backplane data link. Decrementing the counter includes the iMS communicating with the iPQ in response to transmitting a cell.

Abstract: A system and method are provided for tolerating data line faults in a packet communications network. The method comprises: serially transmitting information packets from at least one traffic manager (TM); at a switch fabric, accepting information packets at a plurality of ingress ports, the information packets addressing destination port card egress ports; selectively connecting port card ingress ports to port card egress ports; serially supplying information packets from a plurality of port card egress ports; sensing a connection fault between the switch fabric and the TM; and, in response to sensing the fault, reselecting connections between the switch fabric port card ports and the TM. Some aspects comprise: an ingress memory subsystem (iMS) receiving cells on an ingress port exceeding an error threshold. Then, reselecting connections between the port card ports and the TM includes the iMS sending a message to the iTM identifying the faulty ingress connection.

Abstract: A system and method have been provided for translating digitally wrapped communications between networks using different protocols. This invention makes use of an integrated circuit (IC) relay with programmable features to modify the locations and functions of overhead bytes between the receive and transmit sides of the device, permitting two dissimilar networks to be bridged. That is, the IC relay converts frame formatting from one frame structure to another, so that incompatible networks can communicate.

Abstract: A system and method are provided for paralleling data streams in a G.709 network of connected integrated circuits. The system comprises a demultiplexer for receiving a first digital wrapper data stream having a first data rate. The demultiplexer demultiplexes the first data stream into a second plurality of digital wrapper data streams having a second data rate, less than the first data rate. A second plurality of processors each accept a corresponding one of the second plurality of data streams and supply a processed data stream at the second data rate. The demultiplexer receives frame alignment signal bytes in the overhead of every first data stream frame and synchronizes frame alignment signal bytes in each of the second plurality of data streams to the frame alignment signal bytes in the first data stream.

Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the quantity of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols.

Abstract: A system and method have been provided to increase security in scrambled communications by periodically changing the seed masks used to generate the scrambling algorithms at the transmitter and receiver. The scrambling algorithm is changed by periodically modifying the seed masks which establishes the initial state of the scrambling algorithm generators. The same seed mask key is passed through an auxiliary communication channel to the receiver to insure that matching descrambling algorithms are generated.

Abstract: A system and method are provided for generating alarms from forward error correction (FEC) data in a G.709 network-connected integrated circuit. The method includes: receiving messages including forward error correction bytes; using the forward error correction bytes to detect errors in the messages; and, generating alarm signals in response to the detected errors. Generating alarm signals in response to the detected errors includes generating a signal degrade (SD) signal in response to detecting a first number of errors (error density) within a predetermined time period. Likewise, generating alarm signals in response to the detected errors includes generating a signal fail (SF) signal in response to detecting a second number of errors (second error density), greater than the first number, within the predetermined time period. The method further includes: selecting an error type. Then, alarm signals are generated in response to the selected error type.

Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the value of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the quantity, the location, bandwidth, and the bit error rate (BER) of the FSBs.

Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the location of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the number, the value, bandwidth, and the allowable bit error rate (BER) of the located FSBs.

Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper, and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to synchronize the frame structure. The described invention permits the bit error rate (BER) of the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols. This flexibility also impacts the number, the location, bandwidth, and the value the FSBs.

Abstract: A system and method for providing redundancy in an integrated circuit (IC) relay device has been disclosed. The relay device accepts communications on a first and second receive path. The relay device monitors communications on both the receive paths, and selects a path having a high degree of integrity. Likewise, the relay selectively supplies communications on a first and second transmit path. The relay device selects the transmit path having the proper measure of communication integrity. Communications integrity can be based upon internally monitored criteria such as bit error rate, synchronization, clock signals, and forward error correction. Alternately, the integrity is determined external to the relay, and the relay responds to external switch commands.

Abstract: A system and method have been provided to segment communications between relay nodes in a network using digitally wrapped, or frame structure communications. The overhead bytes in the frame are given special functions, to enable processes such as synchronization or an auxiliary communications channel. Overhead byte quantities, locations, values, or combinations of the above are used to signal the processes. Nodes in the network can be selectively programmed to recognize the overhead byte signals that trigger the processes.

Abstract: A system and method have been provided for programming synchronization features of a multidimensional digital frame structure. Such a frame structure acts as a digital wrapper and includes overhead, payload, and forward error correction (FEC) sections. Words in the overhead section are used to selectively synchronize the broadcast frame structure at a plurality of network nodes. The described invention permits the frame synchronization bytes (FSBs) to be made programmable, so that the system and method are flexible for changes in communication protocols, as well for the selective exclusion of nodes. This flexibility also impacts the number, the location, bandwidth, and the bit error rate (BER) of the located FSBs.

Abstract: An integrated circuit relay device and switching method are presented that permit communications to be routed in a variety of patterns so that diagnostic procedures can be performed in situ, to evaluate digital wrapper communication links. The relay has a pair of inputs, a pair of outputs, a decoder, and an encoder. The relay is programmable to operate in a variety of modes, so that communications can be passed between any set of ports, with or without encoding and decoding processes. The flexible relay routing permits either test signals or normal communications to conducted through the device.