Abstract: A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data block associated with a first address and a second data block associated with a second address. In response, the slave device may send to the master device a portion of the first data block in a first burst and a portion of the second data block in a second burst via a plurality of bidirectional data paths. The slave device may further generate and send to the master device via one or more unidirectional data paths a cyclic redundancy code (CRC) based upon the first data block and the second data block.

Abstract: A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.

Abstract: A memory system includes one or more memory units, each including one or more memory devices and a parallel interconnect. The system also includes a memory controller that may control data transfer between the memory controller and the memory units. The memory system further includes one or more buffer units that are coupled to the memory units via the parallel interconnect. Each of the buffer units is coupled to the memory controller via a respective serial interconnect. Each buffer unit may, in response to receiving command information from the memory controller, receive data from the memory controller via the respective serial interconnect, and also transmit the data to the memory units via the parallel interconnect. The memory controller may further asymmetrically control data transfer between the memory controller and the buffer units by adjusting signal characteristics of transmitted data based upon information received from the buffer units.

Abstract: A system including a single ended switching topology for high-speed bidirectional signaling includes a device coupled to a plurality of bidirectional signal paths. The device includes a plurality of voltage mode driver circuits, each coupled to a respective signal path. Each of the driver circuits may source a voltage when transmitting data and terminate a respective signal path to a ground reference when receiving data. The device also includes a shunt regulator circuit coupled to a voltage supply of the device. The shunt regulator may provide a current shunt from the voltage source to the ground reference in response to detecting a transition on the voltage supply in which the voltage increases above an average DC voltage.

Abstract: A system for controlling high-speed bidirectional communication includes a slave device such as a memory device, for example, coupled to a master device such as a memory controller, for example. The master device may be configured to control data transfer between the master device and the slave device. The master device may be configured to provide one or more clock signals to the slave device and during an initialization mode, the master device may modify a phase alignment of the one or more clock signals. Further the master device may subsequently modify a phase alignment of data transmitted from the master device based upon information received from the slave device.

Abstract: A technique for characterizing a communications interface includes determining a voltage margin and a timing margin of the interface based on data sampled by a sampling device of a receiver of the interface. In at least one embodiment of the invention, a method for determining margin associated with a receiver circuit of an integrated circuit includes periodically sampling a signal over a time period by a receiver sampling circuit of the receiver circuit to generate a sampled version of the signal. The method includes incrementally varying a value of the parameter associated with the signal. The varying of the parameter is through a range of values of the parameter over the time period. The method includes determining a margin value of the receiver circuit associated with the parameter based, at least in part, on the sampled version of the signal.

Abstract: A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimizing a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

Abstract: An in-band configuration technique configures a data communications link for high-speed data communications between at least a first and second integrated circuit using in-band communications between the first and second integrated circuits. The technique configures at least one equalizer of the data communications link with predetermined equalizer settings selected from a plurality of predetermined equalizer settings based on a selected rate of data communications for the link.

Abstract: A clock phase recovery circuit in a communications receiver generates a sample clock signal for recovering data from a received data signal. The sample clock signal is based at least in part on phase difference information associated with the received clock signal and the received data signal. The received clock signal and received data signal are separately received by a receive interface circuit from a transmit interface circuit over a data communications link. Transmit clock jitter is effectively a common mode phase variation that is substantially rejected by the clock phase recovery circuit. Accordingly, the transmit clock jitter can be greater than otherwise allowable.

Abstract: A driver circuit. In one embodiment, the driver circuit includes a plurality of pull-up circuits and a plurality of pull-down circuits. The driver circuit also includes control logic that is coupled to activate/deactivate the pull-up and pull-down circuits. The driver circuit may perform emphasized signal transmissions having a voltage swing of a first magnitude or de-emphasized signal transmissions having a voltage swing of a second magnitude, wherein the first magnitude is greater than the second magnitude. The control logic is further configured to activate and/or deactivate pull-up and/or pull-down circuits such that the driver circuit output impedance in the emphasized mode is substantially equal to the output impedance in the de-emphasized mode.

Abstract: A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

Abstract: A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer.

Abstract: A low latency method of synchronizing asynchronous data to a core clock in a receiving device. A communication referenced to a transmitting clock that is asynchronous to the core clock is received at a receiving device. The communication includes a synchronization signal which is propagated through a synchronizer in the receiving device to synchronize the signal to the core clock. Upon receipt of the synchronization signal by the synchronizer, a load pointer for loading received data into a buffer synchronous with the transmitting clock is reset. Upon completion of the propagation of the synchronization signal through the synchronizer, an unload pointer for unloaded the data from the buffer synchronous with the core clock is reset. The unload pointer is then offset by an amount that compensates for the delay incurred while the synchronization propagated through the synchronizer.

Abstract: A color graphics control system for generating red, blue and green analog signals to a raster scan display at a pixel frequency comprises a RAM storing a pluraltiy of digital color values, digital to analog converters for converting the digital color values into analog signals, an interface to permit an external controller to write digital color values into the RAM locations, a timer including a pixel clock and RAM accessing means controlled by the timer to pipeline RAM accessing with a cycle time of more than one pixel period.

Abstract: An integrated circuit device includes a timing apparatus arranged to produce timing signals whose frequency is a multiple of that of a clock signal. The timing apparatus, which includes a phase locked loop, is formed on a single chip and no external components are necessary. The phase locked loop includes a convertor and filter circuit (11), the convertor (14) including two transistor current sources (19,24) whose current magnitude is determined by a current reference circuit (13) including current mirror transistors (28, 31). The current sources (19, 24) are controlled by increase and decrease output signals from a phase and frequency comparator (7) such that the output of the convertor (14) depends upon the mark space ratio of the comparator output signals. The output of the convertor (14) is filtered and then fed as a control voltage to a voltage controlled oscillator (12).