Abstract: A multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells positioned above the substrate layer. Each photovoltaic cell has a top contact layer and a bottom contact layer connected in series such that the top contact layer of the first photovoltaic cell is connected to the bottom contact layer of a next photovoltaic cell until the last photovoltaic cell is connected. A different voltage is output between the substrate layer and the top contact layer of each photovoltaic cell. Another multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells stacked vertically above the substrate layer. Each photovoltaic cell comprises an active layer separated from the next photovoltaic cell by an etch stop layer until a last photovoltaic cell is reached. A different voltage is output between the substrate layer and the active layer of each photovoltaic cell.

Abstract: Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Abstract: A method (and structure) includes receiving a challenge for an authentication, in a chip having stored in a memory device therein a secret to be used in an authentication attempt of the chip by an external agent. The chip includes a hardware processing circuit to sequentially perform a processing related to the secret. The secret is retrieved from the memory device and processed in the hardware processing circuit in accordance with information included in the received challenge. The result of the processing in the hardware processing circuit is transmitted as a response to the challenge. The hardware processing circuit executes in a parallel manner, thereby reducing a signal that can be detected by an adversary attempting a side channel attack to secure the secret.

Abstract: A photovoltaic device including a photovoltaic cell and method of use is disclosed. The photovoltaic cell includes at least a first photovoltaic layer and a second photovoltaic layer arranged in a stack. The first photovoltaic layer has a first thickness and receives light at its top surface. A second photovoltaic layer has a second thickness and is disposed beneath the first photovoltaic layer and receives light passing through the first photovoltaic layer. The first thickness and the second thickness are selected so that a first light absorption at the first photovoltaic layer is equal to a second light absorption at the second photovoltaic layer. The photovoltaic cell is irradiated at its top surface with monochromatic light to generate a current.

Abstract: A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.

Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

Abstract: A complementary circuit, including a logic unit which includes pull-up depletion-mode MOS transistors and pull-down depletion-mode MOS transistors and a level shifting circuit coupled to the logic unit.

Abstract: Attach a smart chip to a carrier, and attach a memory chip to the carrier in communication with the smart chip. The memory chip has a larger footprint than the smart chip, overlies the smart chip, and is attached to the carrier by connections around the periphery of the smart chip. Removably attach an energy storage device (ESD) to the carrier and electrically connect the ESD to the carrier via a flex bridge.

Abstract: A photovoltaic device that includes a p-n junction of first type III-V semiconductor material layers, and a window layer of a second type III-V semiconductor material on the light receiving end of the p-n junction, wherein the second type III-V semiconductor material has a greater band gap than the first type III-V semiconductor material, and the window layer of the photovoltaic device has a cross-sectional area of microscale.

Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Abstract: A method of forming a photovoltaic device that includes ion implanting a first conductivity type dopant into first regions of a semiconductor layer of an SOI substrate, wherein the first regions are separated by a first pitch; and ion implanting a second conductivity type dopant into second regions of the semiconductor layer of the SOI substrate. The second regions are separated by a second pitch. Each second conductivity type implanted region of the second regions is in direct contact with first conductivity type implanted region of the first regions to provide a plurality of p-n junctions, and adjacent p-n junctions are separated by an intrinsic portion of the semiconductor layer to provide P-I-N cells that are horizontally oriented.

Abstract: Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

Abstract: A method for forming a pixel circuit includes forming transistors on a substrate; forming a passivation layer over the transistors; forming a contact hole to a source of a transistor; forming a transparent conductor that forms a contact in the contact hole and a resistor to control pixel current; and forming an organic light emitting diode (OLED) with an anode connecting to the resistor.

Abstract: A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.

Abstract: A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Abstract: Attach a smart chip to a carrier, and attach a memory chip to the carrier in communication with the smart chip. The memory chip has a larger footprint than the smart chip, overlies the smart chip, and is attached to the carrier by connections around the periphery of the smart chip. Removably attach an energy storage device (ESD) to the carrier and electrically connect the ESD to the carrier via a flex bridge.

Abstract: A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Abstract: A photovoltaic charging system having a narrow-spectrum light source attuned to an absorption band of a photovoltaic cell may achieve power delivery of at least 0.5 mW/10,000 ?m2 upon stimulation of the photovoltaic cell with narrow-spectrum light.

Abstract: An electrical device that includes a material stack present on a supporting substrate. An LED is present in a first end of the material stack having a first set of bandgap materials. A photovoltaic device is present in a second end of the material stack having a second set of bandgap materials. The first end of the material stack being a light receiving end, wherein a widest bandgap material for the first set of bandgap material is greater than a highest bandgap material for the second set of bandgap materials. A zinc oxide interface layer is present between the LED and the photovoltaic device. The zinc oxide layers or can also form a LED.

Abstract: A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.