Patents by Inventor Gijung Ahn
Gijung Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10116428Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.Type: GrantFiled: May 20, 2014Date of Patent: October 30, 2018Assignee: Lattice Semiconductor CorporationInventors: Qiming Wu, Kai Lei, Fei Song, Kai Zhou, Gijung Ahn, Zhi Wu, Min-Kyu Kim
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Patent number: 9887733Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.Type: GrantFiled: April 28, 2017Date of Patent: February 6, 2018Assignee: Lattice Semiconductor CorporationInventors: Kai Zhou, Shinje Tahk, Kai Lei, Qiming Wu, Gijung Ahn, Min-Kyu Kim, Fei Song, Kexin Luo
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Patent number: 9852103Abstract: Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.Type: GrantFiled: April 8, 2015Date of Patent: December 26, 2017Assignee: Lattice Semiconductor CorporationInventors: Ju Hwan Yi, Young Il Kim, Gijung Ahn, Min-Kyu Kim, Daeyun Shim, Gyudong Kim, Hoon Choi
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Publication number: 20170237464Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.Type: ApplicationFiled: April 28, 2017Publication date: August 17, 2017Inventors: Kai Zhou, Shinje Tahk, Kai Lei, Qiming Wu, Gijung Ahn, Min-Kyu Kim, Fei Song, Kexin Luo
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Patent number: 9673959Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.Type: GrantFiled: September 12, 2014Date of Patent: June 6, 2017Assignee: Lattice Semiconductor CorporationInventors: Kai Zhou, Shinje Tahk, Kai Lei, Qiming Wu, Gijung Ahn, Min-Kyu Kim, Fei Song, Kexin Luo
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Publication number: 20170085359Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.Type: ApplicationFiled: May 20, 2014Publication date: March 23, 2017Inventors: Qiming Wu, Kai Lei, Fei Song, Kai Zhou, Gijung Ahn, Zhi Wu, Min-Kyu Kim
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Patent number: 9479190Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.Type: GrantFiled: October 23, 2014Date of Patent: October 25, 2016Assignee: Lattice Semiconductor CorporationInventors: Kexin Luo, Xiaozhi Lin, Guofu Peng, Yu Shen, Gijung Ahn
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Publication number: 20160254821Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.Type: ApplicationFiled: October 23, 2014Publication date: September 1, 2016Applicant: Lattice Semiconductor CorporationInventors: Kexin Luo, Xiaozhi Lin, Guofu Peng, Yu Shen, Gijung Ahn
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Publication number: 20160248574Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.Type: ApplicationFiled: September 12, 2014Publication date: August 25, 2016Inventors: Kai Zhou, Shinje Tahk, Kai Lei, Qiming Wu, Gijung Ahn, Min-Kyu Kim, Fei Song, Kexin Luo
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Publication number: 20150293879Abstract: Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.Type: ApplicationFiled: April 8, 2015Publication date: October 15, 2015Inventors: Ju Hwan Yi, Young Il Kim, Gijung Ahn, Min-Kyu Kim, Daeyun Shim, Gyudong Kim, Hoon Choi
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Patent number: 8026726Abstract: Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.Type: GrantFiled: January 23, 2009Date of Patent: September 27, 2011Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Gijung Ahn
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Patent number: 7984369Abstract: Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.Type: GrantFiled: January 19, 2007Date of Patent: July 19, 2011Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Hoon Choi, Gijung Ahn
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Publication number: 20100188097Abstract: Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.Type: ApplicationFiled: January 23, 2009Publication date: July 29, 2010Inventors: Chinsong Sul, Gijung Ahn
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Patent number: 7698088Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.Type: GrantFiled: April 30, 2007Date of Patent: April 13, 2010Assignee: Silicon Image, Inc.Inventors: Chinsong Sul, Heon C. Kim, Gijung Ahn
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Patent number: 7500032Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.Type: GrantFiled: August 31, 2007Date of Patent: March 3, 2009Assignee: Silicon Image, IncInventors: Ook Kim, Eric Lee, Gyudong Kim, Zeehoon Jang, Baegin Sung, Nam Hoon Kim, Gijung Ahn, Seung Ho Hwang
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Publication number: 20080114562Abstract: In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.Type: ApplicationFiled: April 30, 2007Publication date: May 15, 2008Inventors: Chinsong Sul, Heon C. Kim, Gijung Ahn
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Publication number: 20080022023Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.Type: ApplicationFiled: August 31, 2007Publication date: January 24, 2008Applicant: SILICON IMAGE, INC.Inventors: Ook Kim, Eric Lee, Gyudong Kim, Zeehoon Jang, Baegin Sung, Nam Kim, Gijung Ahn, Seung Hwang
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Patent number: 7269673Abstract: A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information.Type: GrantFiled: February 18, 2004Date of Patent: September 11, 2007Assignee: Silicon Image, Inc.Inventors: Ook Kim, Eric Lee, Gyudong Kim, Zeehoon Jang, Baegin Sung, Nam Hoon Kim, Gijung Ahn, Seung Ho Hwang
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Publication number: 20070204204Abstract: Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Inventors: Chinsong Sul, Hoon Choi, Gijung Ahn
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Patent number: 7203260Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.Type: GrantFiled: July 3, 2003Date of Patent: April 10, 2007Assignee: Silicon Image, Inc.Inventors: Yongsam Moon, Gijung Ahn, Deog-Kyoon Jeong