Patents by Inventor Gil-heyun Choi

Gil-heyun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • APPARATUS AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICES AND SUBSTRATES
    Publication number: 20120216954
    Abstract: An apparatus and method for fabricating semiconductor devices may increase reliability of the semiconductor devices by decreasing generation of particles and enhancing operation efficiency by decreasing the number of cleanings. The apparatus may include a chamber having a cover plate, susceptors for securely placing semiconductor substrates within the chamber, shower heads located on the cover plate to supply reaction gases into the chamber, and a curtain gas line connected to the cover plate to supply heated curtain gases between the shower heads.
    Type: Application
    Filed: April 30, 2012
    Publication date: August 30, 2012
    Inventors: Jin-ho PARK, Seong-hwee Cheong, Gil-heyun Choi, Sang-woo Lee, Ho-ki Lee
  • SEMICONDUCTOR DEVICE CONDUCTIVE PATTERN STRUCTURES INCLUDING DUMMY CONDUCTIVE PATTERNS, AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20120193792
    Abstract: Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.
    Type: Application
    Filed: September 20, 2011
    Publication date: August 2, 2012
    Inventors: Hei-Seung Kim, In-Sun Park, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee, Jong-Won Hong
  • Method of Manufacturing a Semiconductor Device Having a Porous, Low-K Dielectric Layer
    Publication number: 20120178253
    Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 12, 2012
    Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
  • Structures electrically connecting aluminum and copper interconnections and methods of forming the same
    Patent number: 8211793
    Abstract: A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Myeong Lee, Sang-Woo Lee, Gil-Heyun Choi, Jong-Won Hong, Kyung-In Choi, Hyun-Bae Lee
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    Publication number: 20120153500
    Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: Kyoung-Hee KIM, Gil-Heyun CHOI, Kyu-Hee HAN, Byung-Lyul PARK, Byung-Hee KIM, Sang-Hoon AHN, Kwang-Jin MOON
  • METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
    Publication number: 20120142185
    Abstract: In methods of manufacturing a semiconductor device, a substrate having a first surface and a second surface opposite to the first surface is prepared. A sacrificial layer pattern is formed in a region of the substrate that a through electrode will be formed. The sacrificial layer pattern extends from the first surface of the substrate in a thickness direction of the substrate. An upper wiring layer is formed on the first surface of the substrate. The upper wiring layer includes a wiring on the sacrificial layer pattern. The second surface of the substrate is partially removed to expose the sacrificial layer pattern. The sacrificial layer pattern is removed from the second surface of the substrate to form an opening that exposes the wiring. A through electrode is formed in the opening to be electrically connected to the wiring.
    Type: Application
    Filed: September 22, 2011
    Publication date: June 7, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Lyul Park, Gil-Heyun Choi, Suk-Chul Bang, Kwang-Jin Moon, Dong-Chan Lim, Deok-Young Jung
  • SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20120132986
    Abstract: A semiconductor device includes a substrate having a plurality of horizontal channel transistors formed thereon, an insulation layer structure on the substrate and covering the horizontal transistors, and a plurality of vertical channel transistors on the insulation layer structure.
    Type: Application
    Filed: October 3, 2011
    Publication date: May 31, 2012
    Inventors: Pil-Kyu Kang, Dae-Lok Bae, Gil-Heyun Choi, Suk-Chul Bang, Byung-Lyul Park, Kwang-Jin Moon, Dong-Chan Lim, Deok-Young Jung
  • NON-VOLATILE MEMORY DEVICE
    Publication number: 20120120728
    Abstract: A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.
    Type: Application
    Filed: July 27, 2011
    Publication date: May 17, 2012
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Su-Kyoung KIM, Gil-Heyun Choi, Jong-Myeong Lee, In-Sun Park, Ji-Soon Park
  • Substrate Structure Having Buried Wiring And Method For Manufacturing The Same, And Semiconductor Device And Method For Manufacturing The Same Using The Substrate Structure
    Publication number: 20120108034
    Abstract: Provided are a substrate structure which may solve problems generated in a manufacturing process while having a relatively low resistance buried wiring, a method for manufacturing the substrate structure, and a semiconductor device and a method for manufacturing the same using the substrate structure. The substrate structure may include a supporting substrate, an insulating layer disposed on the supporting substrate, a line-shaped conductive layer pattern disposed in the insulating layer to extend in a first direction, and a line-shaped semiconductor pattern disposed in the insulating layer and on the conductive layer pattern to extend in the first direction and having a top surface exposed to the outside of the insulating layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: May 3, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Lok Bae, Gil-Heyun Choi, Byung-Lyul Park, Pil-Kyu Kang
  • Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers
    Publication number: 20120100708
    Abstract: Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.
    Type: Application
    Filed: July 5, 2011
    Publication date: April 26, 2012
    Inventors: Jae-Hwa Park, Jong-Min Baek, Gil-Heyun Choi, Hee-Sook Park
  • METHOD FOR FORMING LIGHT GUIDE LAYER IN SEMICONDUCTOR SUBSTRATE
    Publication number: 20120088323
    Abstract: A method for forming a light guide layer with improved transmission reliability in a semiconductor substrate, the method including forming a trench in the semiconductor substrate, forming a cladding layer and a preliminary light guide layer in the trench such that only one of opposite side end portions of the preliminary light guide layer is in contact with an inner sidewall of the trench, and performing a thermal treatment on the substrate to change the preliminary light guide layer into the light guide layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: April 12, 2012
    Inventors: DAE-LOK BAE, Byung-Lyul Park, Pil-Kyu Kang, Gil-Heyun Choi, Kwang-Jin Moon
  • Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer
    Publication number: 20120083117
    Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-Heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
  • OXIDATION-PROMOTING COMPOSITIONS, METHODS OF FORMING OXIDE LAYERS, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES
    Publication number: 20120058647
    Abstract: Provided according to embodiments of the present invention are an oxidation-promoting compositions, methods of forming oxide layers, and methods of fabricating semiconductor devices. In some embodiments of the invention, the oxidation-promoting composition includes an oxidation-promoting agent having a structure of A-M-L, wherein L is a functional group that is chemisorbed to a surface of silicon, silicon oxide, silicon nitride, or metal, A is a thermally decomposable oxidizing functional group, and M is a moiety that allows A and L to be covalently bonded to each other.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 8, 2012
    Inventors: Kyung-seok Oh, Kyung-mun Byun, Shin-hye Kim, Deok-young Jung, Gil-heyun Choi, Eunkee Hong
  • CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE, METHOD OF FORMING THE CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE CONDUCTIVE LAYER BURIED-TYPE SUBSTRATE
    Publication number: 20120052635
    Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.
    Type: Application
    Filed: August 30, 2011
    Publication date: March 1, 2012
    Inventors: Pil-kyu Kang, Gil-heyun Choi, Dae-lok Bae, Byung-Iyul Park, Dong-kak Lee
  • Semiconductor Device and Method of Fabricating the Same
    Publication number: 20120043666
    Abstract: For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.
    Type: Application
    Filed: November 2, 2011
    Publication date: February 23, 2012
    Inventors: Byung-Lyul Park, Gil-Heyun Choi, Suk-Chul Bang, Kwang-Jin Moon, Dong-Chan Lim, Deok-Young Jung
  • Method of forming a metal layer and a method of fabricating a semiconductor device
    Patent number: 8119526
    Abstract: A method of forming metal films includes preparing a substrate, on which an insulating layer and a metal layer formed of a first metal are exposed; and forming a metal capping layer by supplying an organic precursor of a second metal onto the substrate to deposit the second metal simultaneously on the insulating layer and the metal layer, wherein the second metal capping layer has different thicknesses on the insulating layer and the metal layer.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 21, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Woong-hee Sohn, Su-kyoung Kim, Gil-heyun Choi, Byung-hee Kim
  • METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING VARIOUS ISOLATION REGIONS
    Publication number: 20120034757
    Abstract: A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.
    Type: Application
    Filed: June 16, 2011
    Publication date: February 9, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Soon Choi, Jun-Won Lee, Gil-Heyun Choi, Eunkee Hong, Hong-Gun Kim, Ha-Young Yi
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20120012969
    Abstract: In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Ho Park, Gil-Heyun Choi, Sang-Woo Lee, Ho-Ki Lee
  • METHOD OF MANUFACTURING A METAL WIRING STRUCTURE
    Publication number: 20120009781
    Abstract: In a method of manufacturing a metal wiring structure, a first metal wiring and a first barrier layer are formed on a substrate, and the first barrier layer is nitridated. An insulating interlayer is formed on the substrate so as to extend over the first metal wiring and the first barrier layer. Part of the insulating interlayer is removed to form a hole exposing at least part of the first metal wiring and part of the first barrier layer. A nitridation plasma treatment is performed on the exposed portion of the first barrier layer. A second barrier layer is formed along the bottom and sides of the hole. A plug is formed on the second barrier layer to fill the hole.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-In Choi, Hyeon-Deok Lee, Gil-Heyun Choi, Jong-Myeong Lee
  • METHOD OF FORMING SEMICONDUCTOR DEVICE
    Publication number: 20110318922
    Abstract: The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok-young Jung, Gil-heyun Choi, Suk-chul Bang, Byung-lyul Park, Kwang-jin Moon, Dong-chan Lim